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Description
A fully integrated radiation-hardened all-digital frequency synthesizer, designed in a commercial CMOS technology, is presented in this paper. Radiation hardness by design is implemented in all analog and digital blocks and throughout the chip architecture. The simulated normalized phase noise is at -230 dBc/Hz, hence outperforms its measured prototype of -210 dBc/Hz. The synthesizer can work with an on-chip crystal oscillator and supports external references between 10-100 MHz. The chip supports 4 differential outputs at various signaling standards up to 1 GHz and 2 differential RF drivers up to 5 GHz. The radiation tolerance was validated on a prototype up to a total-ionizing-dose (TID) level of 100 krad(Si) and a single-event latch-up (SEL) / single-event upset (SEU) level of 62.5 MeV·cm²/mg.
