Mr
Markus Roner
(OHB System AG, Munich, Germany)Mr
Pragoti Pran Bora
(Fraunhofer EMFT, Munich, Germany)
A geostationary satellite typically employs as many as 1000 resistive temperature sensors for its housekeeping activities. These sensors are point-to-point wired to an acquisition unit, which is often a single central interrogator system. This poses a need to develop solutions that can reduce harness complexity and weight while maintaining high reliability and keeping low cost and power consumption of the solution in mind. Digital temperature sensors fabricated as integrated circuits have become a popular choice for use in thermal management systems. The temperature sensor and the digital interface circuitry for bus-type interfaces are integrated on a single chip; thus, enabling modularity and simplicity in the system design. Implementing a sensor network in which the point-to-point connected resistive sensors are replaced with serially connected digital temperature sensors can result in a significant reduction in the amount of wiring. The selection of a suitable technology for designing such sensors is very crucial. The 28 nm Fully-Depleted Silicon on Insulator (FD-SOI) CMOS technology offers many high performance features, namely, faster switching, poly biasing, back-gate biasing for power regulation, and expected latch-up immunity. Additionally, the expected high radiation tolerance of this technology makes it suitable for the development of circuits for space applications. In this paper, we discuss the system-level requirements of a low-power digital temperature transducer application specific integrated circuit (ASIC), currently under development, in the 28 nm FD-SOI CMOS technology from STMicroelectronics. We also present our ongoing work on the chip design. The ASIC will become a part of a low power sensor bus system, to be incorporated in future geostationary satellites, where all the serially connected transducer ICs will communicate with a central interrogator module in a hybrid bus topology. The targeted temperature range of measurement is from -40ᵒC to +125ᵒC with an effective resolution of 0.1ᵒC. A measurement inaccuracy of ±0.5ᵒC is specified for the entire temperature range. On the system-level the ASIC consists of three major design blocks- a band-gap reference based temperature sensor, a sigma-delta analog-to-digital converter (ADC), and a digital serial communication interface. Additionally, circuitries for generation of the internal bias currents and low power digital calibration are included. The sigma-delta ADC has a resolution specification of 14 effective number of bits (ENOB). It is being developed in the scope of the European project called "Thin but Great Silicon to Design Objects" (THINGS2DO). Most of the analog and mixed signal blocks are powered by a 1.0 V nominal supply. For digital input/output (IO) signals a supply voltage between 1.5 V and 1.8 V is required for the IO ring. Different system-level and circuit-level techniques will be exploited to achieve low power operation of the ASIC. Design-level mitigation strategies for non-destructive single event effects (SEE) such as triplicated combinatorial logic and triplicated registers will also be employed. In line with the development of this temperature transducer ASIC, a 1st order sigma-delta modulator and its constituent operational transconductance amplifier (OTA) have been integrated as test structures on an integrated circuit (IC) called "AMBER1". The IC is realized to explore the low power features of the 28 nm FD-SOI technology. It was taped-out in November 2015 and its silicon validation is planned for the mid of 2016.
Summary
We, discuss the system-level requirements of a low-power digital temperature transducer application specific integrated circuit (ASIC), currently under development, with the 28 nm FD-SOI CMOS process of STMicroelectronics. We also present our ongoing work on the chip-level measures to improve design robustness against the harsh environment of the outer space. The targeted temperature range of measurement is from -40ᵒC to +125ᵒC with an effective resolution of 0.1ᵒC. A measurement inaccuracy of ±0.5ᵒC is specified for the entire temperature range. On the system-level, the ASIC consists of three major design blocks- a band-gap reference based temperature sensor, a sigma-delta analog-to-digital converter (ADC), and a digital serial communication interface. Additionally, circuitries for generation of the internal bias currents and low power digital calibration are included. In line with the development of this temperature transducer ASIC, a 1st order sigma-delta modulator and its constituent operational transconductance amplifier (OTA) have been integrated as test structures on an integrated circuit (IC) called "AMBER1". It was taped-out in November 2015 and its silicon validation is planned for the mid of 2016.
Mr
Pragoti Pran Bora
(Fraunhofer EMFT, Munich, Germany)
Mr
Andreas Hurni
(OHB System AG, Munich, Germany)
Mr
David Borggreve
(Fraunhofer EMFT, Munich, Gremany)
Dr
Erkan Isa
(Fraunhofer EMFT, Munich, Germany)
Prof.
Linus Maurer
(Universität der Bundeswehr, Munich, Germany)
Mr
Markus Roner
(OHB System AG, Munich, Germany)
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