Speaker
Mr
Volker Lück
(Tesat Spacecom)
Description
Mixed-signal design allows integration of further external discrete components and hence continues the dividend of integration. However, implementation of a mixed-signal flow into an operating digital or analog design flow is not a straight forward task. In space applications in addition, radiation is always an issue and ways need to be found to mitigate its effect on the circuit. Libraries using modified specialized layouts exist to create rad hard designs for digital and analog functions. Companies offer complete flows from design using pre-designed building blocks to qualified devices using proprietary libraries.
Indeed, these solutions can be very efficient and minimize the risk as used library components might be working in several other designs. However, if application constraints the design to other requirements than implemented within the library cells, full custom solutions might be required to obtain the full benefit of mixed-signal. In addition to the limited availability of analog library cells for space application at the beginning of design, this has been one of the main reasons for the necessity of full custom design in our applications.
Before going mixed-signal, our design flow has been focused on digital designs only and several digital ASICs and FPGAs have been successfully created. One of the main requirements was that the new analog functionality should integrate into the digital flow while preserving it. In addition, our mixed-signal designs usually have a huge amount of digital cells integrated. Consequently, the decision has been to work with a digital-on-top flow. The main design reference is a VHDL-netlist and the final layout is done using a place-and-route tool and not the full custom analog layout tool. This way, the timing information between digital sub-cells like IO-cells, a possible digital core and memory macros is in control of the digital tools and not a full custom designer only. SDF-based verification on top-level remains possible. Furthermore, the exact shape of the digital core can be adjusted easily to fit into the remaining area after placement of the analog macros. Long parallel digital interconnection buses do not have to be drawn manually with a large effort, but are drawn by the place-and-route tool. In addition, this way of designing structure offers to work with analog IPs on the long therm. As a matter of principle, the operation of implementing a memory macro can be similar to the implementation of an ADC for instance. It is instantiated within the digital netlist as a black box, with possible interface description and no dedicated analog tool chain would be required anymore.
The next question is how to obtain a qualifiable rad hard design. Here the approach has been to work with an available commercial process which is tolerant enough for TID and do mitigation for SEE on system and design level rather than modifying the process or its devices. Furthermore, no dedicated rad hard digital standard cell lib should be designed and radiation tolerance should be given at netlist level. This way flexibility to adapt to other processes is retained in principle.
However, not all insufficiencies of the process can be taken care of at system or netlist level. This is why radiation behavior of the process needs to be observed during process choice. Individually checked devices have been whitelisted concerning total dose and SEE behavior. Our result has been, that we can work with our technology applying the netlist mitigation techniques on digital cells. Further devices or macros which might be required, have to be observed, in addition.
3.3 Volts transistors could be used basically without any total dose concerns. Drifts will occur at higher voltage devices. Consequently, they should be avoided where possible and should not be used in analog macros where the exact parameters are important.
On device level, no latch-up issues arose during single event testing. Mitigation techniques for single event effects without dedicated layout are possible. On the digital side we work with triple mode redundancy of memory and logic elements which keeps the devices clean from single events up to a certain threshold. However, as IO-cells might be a bottleneck in this case, we had to develop an own redundant IO cell to keep the complete path redundant.
Digital memory macros implemented as IP cannot be implemented with triple mode redundancy on a low level, as they are fixed. Consequently, they need to be implemented redundant as block and ways to maintain the data have to be applied. This can be a continuous read and write of all memory cells in a certain time. If the data is generated periodically, it needs to be assured, that the time frame is small enough to downsize the probability of an upset.
If latch-ups in IPs like memory macros occur, there are several different methods of treatment. If destructive latch-up occurs during normal operation, the macro cannot be used in normal operation. However, it still might be used for a very short time during start-up for instance as latch-up probability of the system would hardly be affected this way. During normal operation, the macro would need to be disconnected from power. If non-destructive latch-ups occur, it might be possible to power-down one instance of a redundant memory after latch-up detection.
For analog cells, treating SEEs is less straight forward. As we are doing full custom design, we do not know the SEE behavior of the circuits before. We used several approaches in this case. One is to inject charge onto all nodes of few critical circuits during simulations, which is very extensive indeed. Furthermore we work with large time constants at the outputs of DACs for instance. Measured values from ADCs on the other hand are read several times to exclude incorrect measurements. Allowed signal errors due to single events are included inside our specification and the systems themselves are tolerant against short incorrect analog signals. Laser tests are used to get an idea of SEE behavior in early prototyping stages.
With these approaches, we will get rad hard full-custom mixed-signal designs on a commercial process. Next step will be qualification.
Primary authors
Dr
Sebastian Millner
(Tesat Spacecom)
Mr
Volker Lück
(Tesat Spacecom)
Co-author
Mr
Andreas Zoller
(Tesat Spacecom)
Peer reviewing
Paper
Paper files:
