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Edouard Lepape28/11/2023, 09:30
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Edouard Lepape28/11/2023, 09:45
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Alp KILIC (Nanoxplore)28/11/2023, 10:15
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Mr David Merodio Codinachs (ESA)28/11/2023, 12:00
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Mr Sandi Habinc (Cobham Gaisler AB)28/11/2023, 12:30
Frontgrade contribution
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Stephan van Beek (MathWorks), Ms Yanitsa Stoyanova (Airbus)28/11/2023, 14:30
In the ever-evolving field of Field-Programmable Gate Array (FPGA) development, the synergy between advanced design tools and collaborative partnerships holds immense potential. This talk explores the transformative capabilities of HDL Coder, a powerful toolset for generating synthesizable HDL code from MATLAB and Simulink models, and its integration with NanoXplore, a leading provider of...
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Mr Ladislav Řehák (Lauterbach)28/11/2023, 15:00
Collecting code coverage information is required for all the common software certification processes, including the one defined by DO-178C. This is usually a challenge because traditional code coverage measurement requires extensive code instrumentation which has all kinds of side effects like (additional) memory consumption, slowing down the execution, and much more. After discussing the...
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Marti Farras Casas (STAR-Dundee)28/11/2023, 16:00
SpaceFibre (ECSS-E-ST-50-11C) is an evolution of SpaceWire, being backwards compatible with SpaceWire at the packet level. SpaceFibre is a very high-performance, high-reliability and high-availability network technology specifically designed to meet the needs of modern space applications where very high throughput is required. It provides point-to-point and networked interconnections at...
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Pierre Berthet28/11/2023, 16:30
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Klemen Bravhar29/11/2023, 09:30
Nanoxplorer’s Field Programmable Gate Arrays (FPGA) and tools, which help a user integrate their Register Transfer Level (RTL) projects in Nanoxplorer (NX) FPGA portfolio, matured to the point, where a user with few clicks in Graphical User Interface (GUI) Impulse or python environment (NxPython3) build their RTL code for BRAVE FPGAs. The main goal of our practice was to evaluate the latest NX...
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Dr Gerard Rauwerda (Technolution B.V.)29/11/2023, 10:00
The FreNox RISC-V microcontroller IP has its heritage in numerous products for high-assurance and high-reliable security applications for data line encryption and network domain separation (i.e. NLD/EU/NATO-restricted). As a founding member of the RISC-V Foundation, Technolution has designed and implemented the FreNox RISC-V processor family. The FreNox RISC-V microcontroller IP has been...
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Pietro Nannipieri, Pietro Nannipieri (University of Pisa)29/11/2023, 10:30
In recent years, research in the space community has shown a growing interest in AI, mostly driven by systems miniaturization and commercial competition. FPGA have proven to be competitive accelerators for these algorithms and works proposing methods for automating the design on these devices have acquired relevance. The common purpose is to enable a wide range of users without specific skills...
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Luca Sterpone (Politecnico di Torino)29/11/2023, 11:30
Radiation-Hardened-By-Design (RHBD) FPGAs have gained a lot of attention thanks to their excellent compromise between costs and performance. Being of very limited use due to a lack of performance a few years ago, these devices are now capable of implementing a wide range of applications requiring high computational capabilities.
This work describes an implementation of a Very Long...
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Fabrizio Ferrandi (Politecnico di Milano)29/11/2023, 12:00
Europe is working on improving competitiveness in the space services sector by developing radiation-resistant, high-performance microprocessors and simplifying the deployment of complex applications. The HERMES project aims to achieve a technology readiness level of 6 for the rad-hard NG-ULTRA FPGA and supports multicore software programming and FPGA acceleration.
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The talk will focus on the... -
Antonio García Vilanova (FentISS)29/11/2023, 12:30
A comparison of the NG-Ultra high-level performance capabilities in both bare-metal and under the XNG hypervisor for NG-Ultra both in a monocore and in a multicore environment will be carried out, providing valuable insights into a high-degree optimization and unlocking the full potential of this hardware.
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Rubén Domingo Torrijos (GMV)29/11/2023, 14:30
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Mr Thierry Maudire (SYSGO S.A.S.)29/11/2023, 15:00
A brief introduction of SYSGO and its flagship product PikeOS for MPU will be presented, following by a description of the current functionalities available with PikeOS for MPU on the NG-ULTRA development kit platform from NanoXplore: runtime features, as well as development tooling supported. In addition, a live demonstrator featuring PikeOS for MPU running on each of the 4 cores of the...
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