AMICSA 2018

17 Jun 2018, 20:00 → 20 Jun 2018, 16:00 Europe/Brussels

IMEC (Leuven, Belgium)

Boris Glass (ESA), Hilde Derdin (IMEC), Steven Redant (IMEC)

7^th International Workshop on Analogue and Mixed-Signal Integrated Circuits for Space Applications

17^th - 20^th June 2018

Organized in collaboration with ESA, IMEC and our Sponsors, provides an international forum for the presentation and discussion of recent advances in analogue and mixed-signal VLSI design techniques and technologies for space applications.

• Radiation Effects on analogue and mixed-signal ICs
   
• Methodologies for Radiation Hardening on analogue circuits at cell-, circuit-, and system design level
   
• Radiation-hardened technologies for analogue ICs
   
• Radiation tests of analogue and mixed-signal ICs
   
• Qualifying and quantifying radiation-hardness of analogue circuits
   
• Space Applications for analogue and mixed-Signal ICs
   
• Analogue intellectual property and re-usability of analogue circuits in space
   
• Needs and Requirements for analogue and mixed-signal ICs in future space missions
   
• In-orbit Experiences and flight heritage of analogue and mixed-signal ICs

 

 

Proceedings (Revision 1, June 15) AMICSA2018_Proceedings_r1.pdf

Program (Revision 2, June 15) AMICSA2018_Program_r2.pdf

Sunday, 17 June

20:00 → 22:00 Welcome Drink

http://www.cafeentrepot.be/

Monday, 18 June

09:15 → 09:45 AMICSA: Introduction

09:15 Welcome and Introduction

Speakers: Mr Boris Glass (ESA), Mr Steven Redant (imec)

Slides amicsa2018_intro_bg.pdf

09:45 → 11:00 Radiation Effects

Radiation Effects on analogue and mixed-signal ICs

Convener: Dr Sebastian Millner (Tesat-Spacecom GmbH & Co. KG)

09:45 Single Event Effects Analysis in ReadOut Integrated Circuits at Cryogenic Temperatures

**1. Introduction** CMOS technology is widely used in Image sensors and Infrared detector onboard spacecrafts [1]. Actually, many optical applications, like Earth or space observation, the guidance system in a spacecraft (launcher or satellite) are particularly critical. Photonic imager technology has been developed for various wavelengths from ultraviolet, through visible, to infrared. For IR detectors, the MCT material (HgCdTe) is used for the detection circuit. The detection circuit is hybrided on a CMOS circuit which performs the transfer and the control of the IR detector. The CMOS technology used in the readout circuit (ROIC) improves the integration of electronics function. A readout circuit is composed by vertical decoders, multiplexers, sequencer, and various logics and sequential cells. However, these digital CMOS functions of image sensors are known to be sensitive to single event effects (SEE), such as single event transient (SET) or Single Event Functional Interrupt (SEFI) [2]. SETs can be induced by various ionizing particles, i.e., especially heavy ions and protons for the space environment space. The first goal of this paper is to present the impact or not of cryogenic temperatures on SET and SEFI induced by heavy ions on two different readout circuits of IR image sensors developed by Sofradir. The second goal is to analyze the multiplicity of SETs and to determine the origin of such events by the mean of the prediction tool MUSCA SEP3 (MUti-SCAle Single Event Phenomena Prediction Platform) [4-5]. Such analyze is relevant with the aim to anticipate the SEE sensitivity trends and propose new radiation tests protocol for IR detectors. **2. Radiation test of ROIC under heavy ions at cryogenic temperatures** The two readout circuits have been developed by Sofradir and work at 5 V. During the whole SEE tests, the ROIC and its pixel tables was under the heavy-ion beams. The results only characterized the silicon system bare ROIC without MCT attached. The SEE test campaign was performed at UCL with the heavy-ion test facility in Louvain la Neuve, Belgium. Three samples of each readout integrated circuit (ROIC) type were characterized in order to evaluate the device variability. During all the testing measurements, the temperature of the chip was monitored and regulated, by means of dedicated equipment to a range of temperature from 50K to 300K. More details of the radiation setup will be presented in the final paper. Large SET, short SETs, and SEFI were measured during the test campaign. Large and short SETs were defined as a function of the length of the event observed on the VIDEO signal. The multiplicity of SET allowed classifying two more categories: simple and complex SETs. More details will be given in the final paper. **3. SEE analysis** Various SET signatures were identified. These signatures highlighted the difference in term of SEE location: in the pixel array, and on the vertical decoder of the pixel table. A very low sensitivity of SEFI was measured. The multiplicity of the short and large SET events was investigated and analyzed by means of histograms. The two categories of multiplicity were identified depending on the event location: occurrence one up to four SETs is due to an event in the pixel array, while a SEE occurrence with a higher SET multiplicity is due to an event on an adjacent control circuit. This analysis was confirmed by simulations performed with the SEE simulation tool MUSCA SEP3. This point will be fully illustrated in the final paper. Experimental data of short and large SETs obtained for a large range of temperature from 50 up to 300 K during the heavy-ion irradiations highlighted a limited impact of the temperature susceptibility of the two ROICs. The same trend was observed for SEFI. More details and discussed will be proposed in the final paper. Moreover, the results also highlighted a limited impact of the part–to-part variability in the same lot on the occurrence of SET susceptibility at cryogenic temperature for the two ROICs. **4. Conclusion and perspectives** This work presented the analyses of single event transients and functional interrupts measured on two designs of readout integrated circuit under a heavy ions beam cooled down at cryogenic temperatures. The analysis of the multiplicity of SETs in the pixel arrays was completed by means of the SEE prediction tool, MUSCA SEP3. Experimental data confirmed the very limited impact of the cryogenic temperature on SEE occurrence on the two ROICs. These results are consistent with previous simulation results on elementary gates (DFF) [6]. It appears that for this technology used by Sofradir for their ROIC of IR detectors, the future irradiation test campaigns should be realized at room temperature. This allows for reducing the complexity of such irradiation tests during the development of IR detector for a space mission. **References** [1] G. R. Hopkinson, IEEE Trans. Nucl. Sci., vol. 47, no, 6, pp. 2480-2484, Dec. 2000. [2] C. Virmontois, et al, IEEE Trans. Nucl. Sci., vol. 61, no. 6, pp. 3331-3340, Dec. 2014. [3] G. Hubert, et al, IEEE Trans. Nucl. Sci., vol. 56, no. 6, pp. 3032-3042, Dec. 2009. [4] G. Hubert, et al, IEEE Trans. Nucl. Sci., vol. 60, no. 6, pp. 4421-4429, Dec. 2013. [5] L. Artola et al, et al, IEEE Trans. Nucl. Sci., vol. 62, no. 6, pp. 2979-2987, Dec. 2015. [6] L. Artola etal, IEEE Trans. Nucl. Sci., vol. 65, no. xx , pp. xxxx-xxxx, 2018.

Speaker: Mr Laurent Artola (ONERA)

Slides ARTOLA__AMICSA_2018.pdf

10:10 Static Linearity Test for Radiation Effects Characterization of an 18-bit SAR Serial IO COTS ADC: Analog Devices AD7982

This paper reports the testing results of a SuccessiveApproximation-Register (SAR) ADC of 18-bits with Serial Input/Output digital interface. We compare the results of using a standard approach with a new test methodology for SAR static linearity testing. The available test time in between radiation steps is limited in order to avoid annealing. The presented method strongly reduces the amount of output code samples, which implies not only higher test speed but also lower test cost. In high resolution ADCs, performing linearity test using the standard histogram method implies obtaining a large number of samples per code in order to average the measurement noise. This leads to long test time which involve high test costs. Space applications nowadays are trending to the use of COTS devices for cost saving purposes. This is aligned with a reduction in the cost of testing such COTS components. The present work has shown that it is possible to reduce the cost of the linearity test reducing the number of necessary samples. This is done by improving the noise averaging efficiency by using the very accurate input signal information dismissed in the accumulation of the histogram, redistribute the contribution of noise average to all samples and taking care of the high dependence behavior of segmented architectures of some types of high resolution ADCs.

Speaker: Dr Sonia Vargas-Sierra (Alter Technology)

Paper sonia.vargas

Slides Presentacion_AMICSA2018_v3.pdf

10:35 Validation of a High Resolution ADC for Space Applications

We present the test results of a radiation hardened, high resolution ADC for space applications. The ADC is a low-noise, low sampling rate, radiation hardened device optimized to operate in a frequency range from DC to 40kHz. The ADC has been implemented in the 150nm CMOS-SOI process of Atmel following a rigorous design flow and radiation hardening strategy. The ADC features a fully differential analog input voltage interface with a dynamic range of +/-3.3V. A sampling rate of a up to 240kSPS is possible thanks to the selectable Over-sampling Ratio which can be as high as 2048. At low sampling rates, the ADC can achieve a very high SNR of up to 108dB over the entire dynamic range, which is translated to an ENOB of 18bits in terms of noise performance. The static and dynamic performance of the device has been tested in a radiation environment of up to 300krad Total Dose and a maximum LET of 88.4 MeV/mg/cm2 using heavy-ions exhibiting no hard fail, no serious performance degradation or latch up.

Speaker: Mr Kostas Makris (ISD S.A)

Paper AMICSA2018-ISD-Validation_of_ADC_v1.0.pdf

Slides AMICSA2018-ISD-Validation_of_ADC_slides_v1.0-R04.pdf

11:00 → 11:20 Coffee

11:20 → 12:35 Custom Cell-, Circuit-, and System Design: (1/3)

Custom cell-, circuit-, and system design of ICs for space applications Full custom digital, analogue, or mixed-signal: Front-end, Signal processing, Data converters, Receivers and transmitters, Drivers, or other.

Convener: Mr Marc Fossion (Thales Alenia Space Belgium)

11:20 Rad-Hard Telemetry and Telecommand IC suitable for RIU, RTU and ICU Satellite Subsystems

1. Summary/Abstract 2. Introduction 3. Design goals: 3.1. Requirements 3.2. Challenges 4. Architecture analysis: 4.1. Reused IPs 4.2. Block diagram 5. Project milestones 6. Conclusions 7. References

Speaker: Mr Ernesto Pun (ARQUIMEA)

Paper AMICSA2018_epun_et_al.pdf

Slides AMICSA2018_TMTC_RHIC.pdf AMICSA2018_TMTC_RHIC.pptx

11:45 Microchip ATMX150RHA European Mixed Technology for Advanced Designs SAMRH71

Microchip Technology Inc. as a leading provider of microcontrollers for space application design is continuously proposing new devices for the space domain. In addition to an increased power-computing performance, the new generation of microcontrollers integrates more and more advanced analog functions. Use of the ATMX150RHA radiation hardened mixed technology for the development of the new microcontrollers generation allows a high level of system integration. As a reference architecture for mixed system-on-chip, Microchip Technology Inc. is developing the SAMRH71 with integration of ATMX150RHA analog cells in a high performance Cortex M7-based microcontroller. The SAMRH71 embeds a first set of analog functions, mainly focusing the system management features: - linear voltage regulator, including power monitoring features - 32768Hz Internal Oscillator - 32768Hz Crystal Oscillator - 12MHz Internal Oscillator (configurable as 4/8/10/12MHz) - 20MHz Crystal Oscillator To increase the level of integration of such a device, the SAMRH71 embeds 128K of Non Volatile Memory (NVM) and a large set of internal SRAM, thus allowing application running without external memory. The on-chip 128kBytes NVM is built around the ATMX150RHA 32kBytes Flash module . To avoid any electrical influence of the NVM module in the applications that don't require the use of the internal NVM, the SAMRH71 embeds an isolation structure made of ATMX150RHA analog cells. In addition to the isolation of all the IOs of the NVM module, the NVMSWITCHRHA power switch is used to isolate the power supply of the NVM memories from the main SAMRH71 power domains. On the basis of this ATMX150RHA development, Microchip Technology Inc. is working on a derivative of the SAMRH71 reference architecture to provide the market with a smaller device that would integrate more analog cells. This mixed microcontroller will be able to provide advanced functions for control/command applications - 12-bit single-ended / differential multichannel ADC - 12-bit single-ended / differential dual channel DAC - Analog Comparators Taking all the benefits of the IPs developed on the mixed signal ATMX150RHA technology, Microchip Technology Inc. is capable not only to propose a rad-hard technology for ASIC developments, but also to build up advanced controllers that can be disseminated to all the space actors.

Speaker: Hans-Ulrich Zurek (Atmel-Microchip)

Paper AMICSA_Master_ATMX150RHA_MCUs.pdf

Slides Microchip_ATX150RHA_European_Mixed_Technology_for_Advanced_Designs_SAMRH71_AMICSA_18jun2018.pptx

12:10 Status update on GR716 Rad-Hard Microcontroller For Space Applications

ABSTRACT This paper describes the mixed-signal microcontroller GR716 targeting embedded control applications with hard real-time requirements. Prototype devices are currently beeing tape-out in the activity Microcontroller for embedded space applications, initiated and funded by the European Space Agency (ESA). The presentation and paper will describe the mixed digital and analog architecture, performance of the device. This abstract describes an on-going development where the devices are in the stage to be taped-out BACKGROUND Software based data acquisition, dataprocessing and simple control applications are widely used in spacecraft subsystems. They allow implementation of software based control architectures that provide a higher flexibility and autonomous capabilities versus hardware implementations. For this type of applications, where limited processor performance is required, general purpose microprocessors are usually considered incompatible due to high power consumption, high pin count packages, need of external memories and missing peripherals. Low-end microcontrollers are considered more attractive in many applications such as: - Propulsion system control - Sensor bus control - Robotics applications control - Simple motor control - Power control - Particle detector instrumentation - Radiation environment monitoring - Thermal control - Antenna pointing control - AOCS/GNC (Gyro, IMU, MTM) - RTU control - Simple instrument control - Wireless networking In these kind of applications the microcontroller device should have a relatively low price, a low power consumption, a limited number of pins and must integrate small amount of RAM and most of the I/O peripherals for control and data acquisition (serial I/Fs, GPIO’s, PWM, ADC etc.). The requirements for memory and program length are usually minimal, with no or very simple operating system and low software complexity. MICROCONTROLLER ARCHITECTURE The list below summarizes the specification for the complete system: System Architecture - Fault-tolerant SPARC V8 processor with 32 register windows and reduced instruction set - Double precision IEEE-754 floating point unit - Advanced on-chip debug support unit with trace buffers and statistic unit for software profiling - Memory protection units with 8 zones and individual access control - Single cycle instructions execution and data fetch from tightly coupled memory - Deterministic instruction execution and interrupt latency - Fast context switching (PWRPSR, AWP, Register partitioning, irq mapping, SVT, MVT) - Atomic operations support Memories - 192KiB EDAC protected tightly coupled memory with single cycle access from processor and ATOMIC bit operations. - Embedded ROM with bootloader for initializing and remote access - Dedicated SPI Memory interface with boot ROM capability - I2C memory interface with boot ROM capability - 8-bit SRAM/ROM (FTMCTRL) with support up to 16 MB ROM and 256 MB SRAM - Scrubber with programmable scrub rate for all embedded memories and external PROM/ SRAM and SPI memories System - On-chip voltage regulators for single supply support. Capability to sense core voltage for trimming of the embedded voltage regulator for low power applications - Power-on-reset, Brownout detection and Dual Watch Dog for safe operation. External reset signal generation for reseting companion chip - Crystal oscillator support - PLL for System and SpaceWire clock generation - Low power mode and individual clock gating of functions and peripherals - Temperature and core voltage sensor - External precision voltage reference for precision measurement - Programmable DMA controllers with up to 16 individual channel - Embedded trace and statistics unit for profiling of the system Peripherals - SpaceWire with support for RMAP and Time Distribution Protocol - Redundant MIL-STD-1553B BRM (BC/RT/BM) interface - Multiple CAN 2.0B bus controllers - Six UART ports, with 16-byte FIFO - Two SPI master/slave serial ports - SPI4SPACE. Hardware support for SPI protocol 0,1 and 2 in HW - Two I2C master/slave serial port - PacketWire interface - PWM with up-to 16 channels. PWM clock support upto 200 MHz - Up to 64 General input and outputs (GPIO) with external interrupt capability, pulse generation and sampling - Four single ended Digital to Analog Converters (DAC), 12-bit at 3MS/s - Four differential or eight single ended Analog to Digital Converters (ADC) 11-bit at 200KS/s with programmable pre-amplifier and support for oversampling. Dual sample and hold circuit integrated for simultaneously sampling - External ADC and DAC support up to 16-bit at 1MS/s I/O - Configurable I/O selection matrix with support for mixed signals, internal pull-up/pulldown resistors - LVDS transceivers for SpaceWire or SPI4SPACE - Dedicated SPI boot ROM support for configuration Supply - Single 3.3V±0.3V supply or separate Core Voltage 1.8V±0.18V, I/O voltage 3.3V±0.3V

Speaker: Mr Fredrik Johansson (Cobham Gaisler)

Paper GR716-Rad-Hard_Microcontroller_for_space_applications-AMICSA_2018.pdf

Slides CobhamGaisler-GR716-AMICSA18.pdf

12:35 → 14:00 Lunch

14:00 → 15:40 Evaluation and Qualification

Evaluation and qualification of full custom ICs for space applications

Convener: Dieter Herrmann (DLR)

14:00 Re-Thinking Reliability Analysis

Device reliability analysis has evolved little since the release of BERT in 1989, yet the expectations of circuit reliability have changed. While it would be easy to say that the requirements for automotive reliability are the sole factor driving this change, the expected reliability for every application have increased. The average car does not have to sustain the 24 hour a day, 7 day a week that the communication chips in data center need to sustain. The ability of a chip to operate reliably for the expected lifetime of the product is now a major design consideration. There are several challenges when performing reliability analysis. First, there is a need for predictive models. The models that predicted the behavior of micron planar CMOS transistors are not sufficient to predict the degradation for nanometer FinFET transistors. Another consideration is the need to redefine what we mean when we say reliability analysis. Historically BERT and its successors have focused on the device degradation due to electrical stress. This simplistic approach ignores the other factors that can accelerate device degradation, including, device temperature and process variation. Finally, consideration is how reliability simulation is performed. Historically, designers performed a reliability simulation based on their circuit verification testbench run with worst case power supply and voltage conditions. This approach leaves many gaps in the verification, for example, does device degradation cause the device age more quickly or slowly over time? The current approach for analyzing device reliability has not kept with the challenges designers face resulting increased risk of field failures, the very thing reliability analysis is intended to eliminate. In this paper we will explore each of these challenges and then approaches for overcoming them. The first challenge we identified was the need for more predictive device models. Since the original Lucky Electron Model, LEM[], was developed and implemented in BERT more advanced models have been developed, single electron excitation, SEE[], and multiple vibrational excitation, MVE[]. These models offer improvement over the LEM approach but are not sufficient now to support the new device structures required for advanced node designs, for example, FinFET transistors. However, new aging models have been proposed, Xie, et al [], that provide better prediction of HCI induced degradation, as well as, providing more predictive estimation of the BTI induced degradation and recovery. This model is extensible allowing for a unified aging for both legacy and advanced node reliability analysis. The next challenge is to overcome is the definition of reliability analysis. We will look at re-defining reliability analysis so that all the factors that contribute to device degradation are considered together not in isolation. This approach solves the problem of accuracy and creates a new challenge effort, that is, in order to improve the quality of results for reliability analysis, many more simulations will be required. For example, to estimate the effect of process variation on device aging, we will need to run a Monte Carlo simulation and then perform aging analysis on the results. While this simulation is expensive it has a couple of benefits. The first benefit is an accurate estimation of the device degradation due to process variation. The second benefit is that we will understand the design margin, so we can avoid overdesign that results in un competitive products or underdesign that increases the risk of field failures. Another important point is that these improvements in the simulation methodology will result in additional requirements on model extraction. In addition to process variation, approaches for including other phenomena that accelerate device degradation in the analysis will discussed. The final topic will be exploring is the application of mission profiles to reliability analysis. In the context of reliability simulation, a Mission Profile, is a reliability corner. Consider an op-amp, in normal usage the output may swing around the mid-range of the supply voltage and increasing the power supply voltage increases the stress on the transistors but does not significantly impact lifetime. Yet if in the application when the op-amp is switched of and the output floats to VDD, full supply voltage would be applied to the compensation capacitor potentially causing it to fail in a much shorter time. Using Mission Profiles allows us to explore how the different competing degradation mechanisms impact the design in order to assure that under all conditions, the device lifetime requirements will be satisfied.

Speaker: Mr Art Schaldenbrand (Cadence Design Systems)

Slides AMICSA_06_18_18_ReThinking_Reliability_Analysis.pdf AMICSA_06_18_18_ReThinking_Reliability_Analysis.pptx

14:25 Digital Programmable Controller (DPC) : radhard die in low cost plastic package

The presentation covers the lessons learned from introduction of the Digital Programmable Controller ASIC (DPC) into several space products. Full benefit of DPC introduction, like decentralization of equipment management, is currently limited by size & cost of the component, the latter being a key factor for constellations. Alternative packaging trade-offs will be discussed: a non-hermetic BGA type package has been prototyped. Pro & con of the hermetic & non-hermetic options will be discussed including the associated TRL levels.

Speakers: Mr Alain Van Esbeen (Thales Alenia Space Belgium), Mr Marc Fossion (Thales Alenia Space Belgium)

Paper HMCU-XR-2088-01-00-AMICSA2018_article.pdf

Transparents TASB-XR-2094-01-00-AMICSA-2018-BGA.pdf

14:50 ESCC Single Phase Qualification

As advanced at previous communications at AMICSA 2012 and 2016, the European Space Components Coordination (ESCC) system has evolved in recent years in order to adapt its methodologies for Qualification. The most recent developments of possible interest for the AMICSA community may be: - the recent approval by the ESCC Policy and Standards Working Group of a so-called Single Phase Qualification (SPQ) approach for microcircuits - the launch of a working group aimed at delivering in 2018 a new scheme for the certification of Assembly and Test Houses (ATH) This paper will describe the principles of implementation SPQ as set in the forthcoming update of ESCC 9000 and the progress in the preparation of the ATH certification scheme. A special focus may be set on new opportunities (new product, new suppliers, a "controlled shortcut" to full Qualification ) which open up now that these developments are underway. The paper will provide as well a summary of the basic requirements applicable to any ESCC Qualification so the AMICSA audience may understand better whether there is anything in it for their activities and products

Speaker: Mr Fernando Martinez (ESA)

Slides SPQ_at_AMICS2018_final.pptx

15:15 Characterization, Screening and Qualification of the MEDA Wind-Sensor ASIC

The paper describes the final characterization results of the MEDA-WS ASIC, which was described in a previous paper in AMICSA-2016. It describes as well the qualification and the screening processes that have been carried out, and the present status of its integration and calibration in the final engineering and flying modules of the wind-sensor instrument. Specific details include to the low-temperature and radiation tests, the final packaging and its qualification implications, as well as some thermal behavior considerations. The paper begins with a brief review of the ASIC description and functionality, as well as the circuit techniques employed for its different circuit blocks and the RHBD techniques used. Although the ASIC fulfils the prescribed specs and accuracy figures, and will be used "as is" in the instruments to be sent to Mars, a few sources of minor accuracy deviations that have been identified will be described together with their eventual future correction in other versions of this or other similar ASICs.

Speaker: Mr Servando Espejo (IMSE-CNM-CSIC / Universidad de Sevilla)

Slides AMICSA-2018-presentacion.pdf

15:40 → 16:00 Coffee

16:00 → 16:50 Custom Cell-, Circuit-, and System Design: (2/3)

Custom cell-, circuit-, and system design of ICs for space applications Full custom digital, analogue, or mixed-signal: Front-end, Signal processing, Data converters, Receivers and transmitters, Drivers, or other.

Convener: Mr Michael Kakoulin (IMEC)

16:00 A radhard LVDS chip: transistor level design aspects

A radhard space-grade LVDS dual transmitter chip is designed. The functionality includes high input common mode voltage (-4 to 5V), high ESD immunity (8 kV), active failsafe operation (for Rx), and cold spare. To be able to realize this, at transistor level several novel techniques had to be applied; this paper will highlight several of these. **Rx**: failsafe: a novel architecture is used, in order not to violate an existing patent. The output of a peak detector is compared to the average value of the signal, taken the failsafe detection limit into account through a resistive reference voltage to current to detection voltage transformation. Failsafe is only activated then when the condition exists for a minimum period. Benefit is made of triple well NMOS transistors, as they allow to avoid bulk effect, resulting in an elegant circuit. **Rx**: the Rx digital output pin is next to the Rx input (prerequisite of the pin diagram, for compatibility reasons). For high CMIR, the LVDS input signal differential voltage is divided by five (by an all-pass filter). Even small parasitic couplings between the output and the input (off and on chip) then potentially result in a system that oscillates, and hence several measures are taken to avoid this: two delays are inserted in the failsafe circuit, filtering input noise&glitches, but such that they do not jeopardize the functional operation: 1. a minimum signal/glitch duration to leave failsafe and 2. a minimum failsafe duration. Receiver hysteresis is implemented in a clever way: the hysteresis is only active when Rx is not in failsafe; again this filters glitches that might appear at the Rx input. **Also, the Rx (two pins) ESD protection**: 8 kV HBM requires a big protection, which is towards gnd. Hence gnd noise from LVTTL digital output switching is coupled directly into the Rx’s (sensitive) input, and this loop easily might oscillate; this compromised the ESD protection design; solution will be shown. **Tx**: common mode regulation: classically the common mode is sensed using a differential output resistor. However this results in an extra uncertainty in the LVDS output current. In this design the common mode is sensed by a differential difference amplifier, which does not draw any input current. **LVTTL digital input**: 5 V input range combined with cold spare (“no VDD”) required the use of some ingenious circuitry to be able to accommodate all possible conditions.

Speaker: Mr Jan Wouters (Imec)

Paper A_radhard_LVDS_chip_transistor_level_design_aspects_Amicsa2018_JWouters.pdf

Slides A_radhard_LVDS_chip_transistor_level_design_aspects_Amicsa2018_JWouters_slides.pptx

16:25 Correlators for Interferometric Radiometry in Remote Sensing Applications, A Scaling Perspective

Correlators are extensively used in the field of radio interferometry. Two different types are considered for two applications; autocorrelators for spectrometry and cross-correlators for aperture synthesis. We concentrate on satellite-based applications where power budgets are very restrictive. Several satellites are already employing correlators for interferometric measurements, and future projects are targeting even larger systems in terms of spectral channels in the case of spectrometry and baseline counts in the case of aperture synthesis. Thus, it is important to develop correlators with increasing channel count, either using ASIC technology scaling or by constructing larger systems from several ASICs. Building on earlier ASIC designs, we examine how larger correlator systems can be constructed and the implications this has, in terms of power dissipation, system complexity, and ASIC count. Our findings indicate that, for large systems, having a very high channel count per ASIC is indeed of interest for keeping system complexity and power dissipation down by reducing both ASIC and I/O count, especially for cross-correlators.

Speaker: Mr Erik Ryman (Omnisys Instruments AB)

Paper AMICSA2018_ryman.pdf

Slides Presentation.pptx

16:50 → 20:05 AMICSA: Guided Tour and Welcome Reception

16:50 Leuven Guided Tour

19:00 Welcome Reception

Tuesday, 19 June

09:15 → 10:00 Keynote Speach: (1/2)

09:15 Functional Safety Management in the automotive world and beyond?

ISO 26262 is an automotive standard that was released in November 2011 and has as target to make cars safer. This point is especially important when thinking about the actual trend towards more and more autonomous cars where the amount of safety critical electronics is increasing quickly and where the impact of potential safety critical failures is very high. Wrong decisions taken by the electronic systems can have an important impact on the people inside and outside of the car. The purpose of the standard is, by focusing on systematic and random hardware failures, to help reducing the risk of safety critical malfunctions to an acceptable level. The standard proposes to achieve this through a series of work products and through robust design methods of the system itself and its electronic sub-components. The target of this presentation is to give a quick overview of the purpose and content of the standard and to explain how it relates to semiconductor mixed-signal developments. A general flow will be presented which starts from a safety concept and ends with an architecture that achieves a high diagnostic coverage. The core of the presentation will be dedicated to explaining the challenges to perform a functional safety analysis according to ISO 26262 and present the work products that are recommended by the standard. Also some time will be spent during the presentation to explain the impact of the safety analysis on the architecture of the component under development and to understand when enough has been done to make the device safe.

Speaker: Mr Yves Renard (ON Semiconductor)

10:00 → 10:50 Space Applications: (1/2)

Space applications for analogue and mixed-signal ICs Power handling, distribution and control,instrumentation, actuation, imaging, communication and navigation, or other.

Convener: Mr Jose F. Moreno-Alvarez (Airbus Defence and Space)

10:00 SIS20: A CMOS ASIC for Solar Irradiance Sensors in Mars Surface

This paper reports the design and characterization of the ASIC SIS20, planned for an instrument aimed to measure Solar Irradiance on the surface of Mars. It has been designed using the AMS0.35u CMOS technology and with the rad-hard digital library developed at IMSE (Spain). The ASIC is intended for flying with the ExoMars2020 mission. The design was taped out in June2017. Samples are packaged in a 68 pins module. Nowadays, a complete functional testing in the specified range of temperature (-125º C to 50º C) has been carried out for several samples. Figure 3 shows the PCB Test Board. Results are in accordance with the specifications. At this moment, the chips are under the qualification process. Of course, if accepted, the final paper would summarize the results from the lab.

Speaker: Prof. Vázquez Diego (IMSE-CNM-CSIC/University of Seville)

Slides Presentacion_Amicsa2018.pptx

10:25 Ultimate earth observation using time delay integration line scan imagers using the CCD-in-CMOS technology

Imec has been developing a combination of CCD and CMOS technology in one process flow. This enables low noise time delay integration (TDI) line scanners including the signal drivers and readout circuit on-chip – which is not possible using CCD imagers. In combination with spectral filters integrated on-chip, this allows high resolution and spectrally resolved earth observation from low orbit (e.g. micro-)satellites. The imec developments, e.g. 7 band CCD-in-CMOS TDI device will be discussed.

Speaker: Dr Piet De Moor (imec)

Paper AMICSApaperPietDeMoor.pdf

Slides AmicsaPdM.pptx

10:50 → 11:20 Coffee

11:20 → 12:35 Space Applications: (2/2)

Space applications for analogue and mixed-signal ICs Power handling, distribution and control,instrumentation, actuation, imaging, communication and navigation, or other.

Convener: Mr Jörg Ackermann (Integrated Detector Electronics AS)

11:20 Channeltron Detector Readout ASIC in 0.35μm HV CMOS for Cold Solar Wind Analysis

The content of the paper focuses on the design of analog front-end readout circuits for Channeltron detectors in 0.35µm CMOS technology for the Cold Solar Wind Analysis.

Speakers: Prof. Hélène TAP (INP-ENSEEIHT LAAS), Ms king wah wong (IRAP CNRS)

Paper AMICSA-THOR-2018_V1p0.pdf

Slides AMICSA-2018-V2.pptx

11:45 A Fault Tolerant PMAD System Using Radiation Hardened Highly Integrated AFE Integrated Circuits

Abstract ======== Fault tolerance of power management and distribution (PMAD) systems in a radiation environment is one of the important characteristics for the reliability of spacecrafts. Furthermore, using highly integrated ICs in the PMAD design leads to lower footprint, therefore it is advantageous to consider the design of redundant PMAD system using ICs that offer a high degree of integration. This paper describes a PMAD topology using series MOSFETS driven by a single AFE IC that implements sense and control interfaces to the power devices. Special attention is given to the aspects of parametric drift due to radiation effects on the AFE and a method of how system design can alleviate its effect is shown. In conjunction with an FPGA, the AFE sub-system can run MPPT on multiple strings of photovoltaic modules and deliver power to the main power distribution bus. Additional protection circuits manage power distribution to loads and to and from a battery unit. The PMAD topology ================= The PMAD system needs to optimally transfer power from the input sources and manage transmission of power to loads and to and from the battery system. It mainly consists of DC/DC converters, protection circuits and a power transfer and fault management function that is partly local and partly remote. In our proposed topology, the inputs are assumed PV module strings for which a fast and accurate MPPT control [1] needs to run in order to track varying angle /shading /temperature condition per string. Thus, several boost DC/DC power converters seek independently MPP per string while driving the power distribution bus. Voltages on input and output nodes and currents through each converter are monitored and used to control each DC/DC converter. Additionally, temperature is monitored at key points and AFD what is AFD? circuits are used to detect arc on each high current/voltage rail. Control is done digitally: - an analog front end is used to convert to digital all sense lines and to drive MOSFETs from digitally generated PWM - an FPGA implements the DC/DC control, MPPT and power and safety management A communication function can also be implemented for the remote function. The connection of loads to the power distribution bus is done via individual current / SOA protection circuits that interface with the same FPGA (see figure 1). Figure 1. The PMAD block diagram Fault tolerant power stage control ================================== The DC/DC boost unit converter is implemented using a series connection of two NMOS transistors for each high and low side. This way the controller can disable both high and low side paths in case of short circuit developing in one of the four MOSFETs at the expense of some converter efficiency loss (see figure 2). During regular switching periods the upper most (M11 and M21) and lower most (M14 and M24) MOSFETs are ON all the time while the mid MOSFETs (M12, M13, M22 and M23) are switching. From time to time, switching is exercising the upper most and lower most MOSFETs to verify their health state while the mid MOSFETS are turned ON continuously. If shoot-through current or inductor current sensors detect a large change when moving from mid to upper most and lower most MOSFETs a fault is identified and the power stage is disabled and a redundant power stage is enabled (e.g. Boost 11 is disabled and Boost n1 is enabled in figure 1). The analog front end can sense both inductor and shoot through current if any. The shoot through current measure is based on a difference measurement: first the switching is done with enough dead band to guarantee no shoot through current and the peak current is measured, then, in the next switching cycle, the timing to be measured is applied and the peak current is measured again. The difference between these measurements is a measure of the timing dependent shoot through current. The controller averages this measure to eliminate input or output transient influence on the measurement. The shoot through current, together with a conversion efficiency measure (using input and output currents and voltage sense) are used by the FPGA-based controller to fine-tune the MOSFETs timing to compensate for any long term radiation induced timing drift. Figure 2. The DC/DC boost fault tolerant power stage Using an integrated AFE as PMAD element ======================================= Traditionally, LX7720 (see figure 3) [2] is used in motor control applications where it drives the power MOSFETS for the motor and solenoid control and acquires output currents and a resolver interface. However most of the LX7720 can be used in other power control applications. Particularly, in this PMAD system application, we use three voltage sense ADC channels (Vin1, Vin2 and Vbus – see figure 2) and four current sense ADC channels are used to sense the inductor current (via Rs10 and Rs20) and shoot through current (via Rs11 and Rs21) for two fault tolerant power stages. Four high side / low side pairs of gate drivers are used to drive all 8 MOSFETS (M11-M24) required to implement the two fault tolerant power stages. The LX7720 internal charge pump is activated to turn permanently ON the upper most side MOSFETs (M11 and M21) connected directly to the rail. Additionally, the LX7720 resolver driver outputs are used to drive the primary of an isolated DC/DC converter to power auxiliary circuits for arc fault detection. A good power ground versus signal ground rejection makes this circuit operate well in this power control application. Figure 3. LX7720 block diagram detail Other system implementation aspects =================================== The LX7712 [3] is a power line protection device that is used for spacecraft power distribution. It provides a means to turn on or off a DC load with current up to 5A. The LX7712 is an integrated circuit which includes a solid-state P Channel MOSET switch and catch diode (see figure 4); integration allows the temperature of the switch to trigger an optional thermal shutdown. It can be configured as a latch-able current limiter or a fold-back current limiter. Multiple devices can be paralleled in a master/slave arrangement to increase the current rating. Figure 4. LX7712 block diagram The full paper will describe in more detail the application of this rad tolerant power line protection device. The FPGA implements several state machines to operate each LX7720 AFE: - 2 PID controllers to operate the two DC/DC converters - 2 maximum power point tracker state machines - 2 shoot-through / timing optimizer state machines - 2 fault detection and fault management state machines Beside these the FPGA must run load control and communication functions to orchestrate the PMAD operation. A more detailed description of the FPGA based control strategy will also be given. Conclusions and future work =========================== A new application for an IC traditionally used in actuator control is described. Based on the novel usage, LX7720 implements the analog front end of a PMAD system. A technology demonstrator is being built and measurement results will be available by the time of publishing. References ========== [1] S. A. Spanoche, J. D. Stewart, S. L. Hawley and I. E. Opris, "Model-Based Method for Partially Shaded PV Module Hot-Spot Suppression," in IEEE Journal of Photovoltaics, vol. 3, no. 2, pp. 785-790, April 2013. [2] LX7720, Rad Hard Spacecraft Power Driver with Rotation and Position Sensing, Datasheet, Microsemi Corp. (available upon request) [3] LX7712, Rad Tolerant Power Line Protector Device, Datasheet, Microsemi Corp. (available upon request)

Speaker: Mathieu Sureau (Microsemi Corp.)

Slides sorin.spanoche@microsemi.com

12:10 A rad-hard systems-on-chip solution for close-loop motor control

This paper describes the design and implementation of a systems-on-chip solution for close-loop control of remote-handling robotic tools in radiation environment. The original intended application of the development is for remote handling equipment at ITER (a first-of-kind Tokamak fusion nuclear plant). Front-end electronics that located close to sensors and actuators on ITER remote handling systems will face gamma radiation up to 300 Gy/h and a total dose of 1 MGy, and total neutron fluence up to 10¹⁵ n/cm². Hence those electronics are required to be radiation-hardened against total-ionizing-dose (TID) radiation, as well as single-event effects (SEE) caused by neutrons (14 MeV). In order to broaden the application scope of the system, the chips were also designed to be resistant against higher energy particles (e.g., >60 MeV protons and heavy ions). The close-loop motor control system consists of five ASICs:

• A resolver/LVDT to digital converter to read out angle information from a resolver or linear distortion information from a LVDT.
• A resistive bridge sensor signal conditioning ASIC to read out sensors such as RTD, thermocouple, and strain gauge.
• A 24V 10-channel limit switch conditioning ASIC to read the status of limit switches connected to it.
• A 24V 10-channel relay driver ASIC to drive high-side solid-state or mechanical relays.
• A bus communication ASIC to implement the BiSS interface protocol, the SPI master protocol, and the RS485 bus transceiver.

Those ASICs are implemented in two commercial CMOS technologies: a low-voltage 65nm CMOS process and a 0.35µm high-voltage CMOS process. Radiation-hardened-by-design (RHBD) techniques are used in the design of the ASICs to against both TID and SEE, such as:

• use dynamic compensation techniques to mitigate radiation-induced performance drifts;
• use enclosed-layout transistors to reduce radiation-induced leakage currents;
• use guard-rings to mitigate inter-device leakage;
• use radiation-aware transistor sizing to limit radiation-induced threshold voltage shift;
• use guard-rings and of abundant contacts for all wells to mitigate single-event-latchup;
• use triplication and voting for all digital circuits to mitigate single-event-upset;
• use averaging and filtering in analog circuits to reduce single-event-transient.

The potential space applications of the close-loop motor control system could be:

• control of remote handling manipulators and remote operated vehicles;
• speed control of reaction wheels;
• control of electrical propulsion system;
• altitude control of spacecraft and satellites;
• control of electrical valves.

Speaker: Dr Ying Cao (MAGICS Instruments)

Paper MAGICS_AMICSA_2018_v3.pdf

Slides magics_amicsa2018_ppt (Protected) magics_public

12:35 → 14:00 Lunch

14:00 → 16:00 Industrial Presentations

14:00 Alter Technology

Speakers: Dr Sonia Vargas-Sierra (Alter Technology), Mr xavier wiedemann (Alter Technology)

14:00 Arquimea

Speakers: Mr Daniel Gonzalez (Arquimea Ingenieria S.L.U), Mr Ferran Tejada (ARQUIMEA DEUTSCHLAND GmbH)

14:00 Atmel/Microchip

Speakers: Mr Erwann BERLIVET (Atmel/Microchip), Ms PASCALE CHARPENTIER (MICROCHIP Aerospace and Defense Business Unit)

14:00 Cobham

Speaker: Teresa Farris (Cobham)

14:00 IHP

Speaker: Judith Kroel (x)

14:00 imec

14:00 Magics Instruments

Speaker: Dr Ying Cao (MAGICS Instruments)

14:00 Microsemi

14:00 Micross

14:00 Microtest

14:00 Renesas

Speaker: Mr Oscar Mansilla (Intersil)

14:00 Renesas

Speaker: Mr Oscar Mansilla (Intersil)

14:00 Serma/HCM Systrel

Speakers: Mr Frédéric OUDART (SERMA Group), Mr Maxence LEVEQUE (SERMA Group)

14:00 Teledyne e2v

Speakers: Ms Lynn Todd (Teledyne e2v), Dr Romain PILARD (Teledyne e2v)

14:00 Thales Alenia Space Belgium

Speakers: Mr Alain Van Esbeen (Thales Alenia Space Belgium), Mr Marc Fossion (Thales Alenia Space Belgium)

14:00 → 16:00 Poster: Custom Cell-, Circuit-, and System Design

14:00 Radiation Hardened Pulse Width Modulator in CMOS-SOI

The aim of this project is to provide Pulse Width Modulator controller solution that will largely simplify Electronic Power Conditioners (EPC) design due to variety of converter topologies that can be realized within one chip and decrease its cost due to integration of more converter elements in one chip. Field of application of our PWM controller can be far greater than EPCs only, ranging from platform to payload units. It can be used in various topologies (Buck, Boost, Buck-Boost, Push-Pull, Flyback and Forward converters) and their synchronous variations. Commonly used regulation control loop is available (voltage mode and current mode). The Pulse Width Modulator ASIC operates with clock signal (externally or internally generated) ranging from 100 kHz to 1 MHz. The internally generated clock is available on an external pin which enables to run other MISAC PWMs for multiphase converters. The clock signal can be shifted by 90, 180 or 270 degrees and can be scaled down up to 8 times. It has one independent voltage reference source (1.25V) and an output pin with an 11mA maximum available current. For PWM signal generation it uses an internal sawtooth generator with its slope trimmable by external components. The Leading edge blanking internal circuit is applied to the current monitoring signal to suppress voltage spikes. The leading edge blanking time, the maximum duty cycle and the minimum duty cycle can be externally configured. Only passive components are needed to for all configurations. PWM output features two 9V to 16V output drivers designed to source and sink high peak currents (up to 2.5A) from capacitive loads, such as the gate of a power MOSFET. The outputs can have four different modes of operation as the needs of the application (single or dual output, alternate, opposite and complimentary). The power supply of the output stage is independent and isolated from the power supply of the rest of the ASIC circuit. Protection circuitry includes a current limiter pulse-by-pulse operation with a 1.25V threshold, a TTL compatible shutdown port, output overvoltage protection circuit and a soft start pin. An under voltage lock-out circuit is used with 600mV hysteresis. The pulse width modulator is implemented in a rad-tolerant 150nm CMOS-SOI process. The ASIC has been radiation-hardened by design techniques (including Triple-Modular- Redundancy, SET filtering, periodic reset with no operation interruption). The project is currently at the start of first samples manufacturing phase.

Speaker: Mr Dimitrios Baramilis (ISD S.A.)

14:00 Radiation-Hard X-Band Phase Locked Loop and Transceiver in 0.25 µm SiGe Technology

I. INTRODUCTION X-band frequencies (8 - 12 GHz) are used for space and satellite communication both in civil and military applications. Traditionally, discrete microwave integrated circuits implemented in III−V technologies have been combined and used for these applications due to their performance advantages over Si technologies [1]-[3]. Unfortunately, such transceiver modules are typically power hungry, large, heavy and hence costly [4], [5]. SiGe HBT technology, being inherently tolerant to TID, good integration capabilities, medium cost and superior performance over Si technology has big advantage for space and satellite communication application. As mostly demanded, a phased locked loop (PLL) chip and a transceiver chip are designed and tested under radiation. The chip details are presented in the following sections. II. PHASE LOCKED LOOP Figure 1 shows the block diagram of the fabricated PLL. The VCO is a differential cross-coupled type using bipolar transistors. The PLL circuit utilizes two tuning loops. The phase frequency detector (PFD) and charge pumps are designed with CMOS transistors. Chip area is 1.22 mmx0.81 mm. Figure 1: Block diagram of PLL chip Table 1: PLL chip performance Parameter Measurement Simulation VCC 2.5 V 2.5 V ICC 32 mA 29 mA VCO tuning range 8 – 11.8 GHz 7.85 – 11.9 GHz PLL locking range 8.192 – 10.56 GHz 8 – 10.7 GHz Output power -3 – +4 dBm 8 – 11 dBm III. TRANSCEIVER Figure 2 shows the transceiver block diagram. It contains voltage controlled oscillator (VCO), power splitter, power amplifier (PA), poly-phase filter (PPF), low-noise amplifier (LAN), quadrature mixer. Built-in system test (BIST) structure is included to test the circuit functionality without antenna and high frequency equipment. Chip area is 1.84 mm x 1.1 mm. Figure 2: Block diagram of transceiver chip Table 2: Transceiver chip performance Parameter Measurement Simulation VCC 3.3 V 3.3 V ICC 153 mA 145 mA VCO tuning range 10.6 – 12.5 GHz 10.1 – 12.0 GHz Output power 8 – 10 dBm 10 – 12 dBm IV. TEST UNDER IRRADIATION The realized chips are tested under Total Dose Ionization (TID) and heavy ion irradiation. TID tests have been performed at Helmholtz-Zentrum Berlin, Germany up to 300 krad. The chips were radiated by Gamma ray from Co60 source. Electrical measurements have been performed after accumulated dose of 25 krad, 75 krad, 150 krad, 230 krad and 300 krad. Finally, after annealing of 24 hours at 25°C and annealing of 168 hours at 100 °C. No noticiable deviation in electrical performance (current, oscillation frequency, receiver gain) have been observed in the test results. Heavy Ion tests including single event latch-up (SEL) and single event upset (SEU) tests are planned in February 2018. REFERENCES [1] C. Drevon, “From micropackages to MCMs up to 40 GHz for space applications,” in IEE Sem. Packaging and Interconnects at Microwave and mm-Wave Frequency, June 2000, pp. 8/1–8/4. [2] A. K. Oki, D. C. Streit, R. Lai, A. Gutierrez-Aitken, Y. C. Chen, R. Grundbacher, P. C. Grossman, T. Block, P. Chin, M. Barsky, D. Sawdai, M. Wojtowicz, E. Kaneshiro, and H. C. Yen, “InP HBT and HEMT technology and applications,” in Proc. Int. Conf. Indium Phosphide and Related Materials, May 2000, pp. 7–8 [3] D. Streit, R. Lai, A. Oki, and A. Gutierrez-Aitken, “InP HEMT and HBT technology and applications,” in IEEE Int. Electron Devices for Microwave and Optoelectronic Applications Symp. Dig., Nov. 2002, pp. 14–17 [4] D. Yamauchi, R. Quon, Y.-H. Chung, M. Nishimoto, C. Romo, J. Swift,R. Grundbacher, D. Lee, and L. Liu, “A compact transceiver for wide bandwidth and high power K-, Ka-, and V-band applications,” in IEEE Microwave Symp. Dig., June 2003, pp. 2015–2018 [5] M. Kärkkäinen, M. Varonen, J. Riska, P. Kangaslahti, and V. Porra,“A set of integrated circuits for 60 GHz radio front-end,” in IEEE Microwave Symp. Dig., June 2002, pp. 1273–1276

Speaker: Dr Wojciech Debski (Silicon Radar GmbH)

Paper Radiation_Hard_PLL_TRX_X-band_SiR_AMICSA_2018.pdf

14:00 SEPHY: a 10/100 Ethernet Transceiver for Space Applications

**SEPHY: a 10/100 Ethernet Transceiver for Space Applications** P. Reviriego, ARIES Research Center, Universidad Antonio de Nebrija, Madrid, Spain J. López, J. Torreño, U. Gutierro, Arquimea, Madrid, Spain A. Breitenreiter, Y. Li, M. Krstic, IHP, Frankfurt (Oder), Germany Topics: Space Applications for analogue and mixed-Signal ICs, Radiation-hardened technologies for analogue ICs **Abstract:** As space systems evolve to become more complex, they need larger computing and communication capabilities. For example, larger data rates must be supported and also more flexible technologies that enable several applications to share the network resources while providing predictable and reliable performance are needed. One of the approaches to address those issues is the adoption of Ethernet in space. This has the benefit of reusing existing and field proven technology that also provides evolution to larger data rates. Ethernet is currently used in some space systems and it is being designed into many others like the next generation of Arianne launchers. Integrated circuits that are used in space systems need to be designed to withstand the effects of radiation that causes errors and failures. These devices known as rad-hard need to be designed and manufactured using specific techniques and processes. Therefore, for Ethernet to be adopted in space, the respective rad-hard Integrated Circuits (ICs) need to be available. The European industry is working on several such ICs including an Ethernet switch and a transceiver. In this paper, SEPHY a 10/100 Mb/s rad-hard Ethernet transceiver designed for space applications is presented. **1. Specifications** The SEPHY transceiver is designed to support 10 and 100 Mb/s over twisted pair cabling as specified in the IEEE 802.3i and IEEE 802.3u standards commonly known as 10BASE-T and 100BASE-TX. The device does not implement the auto configuration features defined in Ethernet like auto-negotiation or the automatic cable crossover. These features are not required since space systems are designed with a fixed configuration and a deterministic behavior is desired. This is just the opposite of home or offices on which ease of use and the ability to add and remove devices is key. Other functional difference to commercial transceivers is that the device implements special registers to count the number of radiation errors detected in the registers and also cold spare capabilities for cold redundancy. Two interfaces for communication with the Media Access Controller (MAC) are supported, the Media Independent Interface (MII) defined in the IEEE 802.3 standard and also the Reduced Media Independent Interface (RMII). In terms of radiation tolerance SEPHY is designed to withstand up to 300 krad to TID and a SEU Bit Error Ratio better than 10-12 at LET>70 MeV/mg/cm². This enables the use of SEPHY chip in most space missions and particularly in launchers and earth orbiting satellites. A key requirement is that the device has no ITAR restriction and to achieve this Microchip 150nm SOI technology targeted to space applications is used. **2. Architecture** The block diagram of the device is shown in Figure 1 where digital blocks are colored in blue and analog blocks in orange. It can be seen that SEPHY chip consists of five main blocks: A MAC interface block, a 10BASE-T digital block, a 100BASE-TX digital block, an Analog Front End (AFE) and a common block. The MAC interface implements both MII and RMII at 10 and 100 Mb/s. The 10BASE-T and 100BASE-TX blocks implement the transmitters and receivers for both standards. The analog front end is in charge of converting the analog signals received from the cable to digital on reception and the other way around for transmission. Finally, the common block contains both analog and digital functionality that is used in complete device providing clock and reset and the configuration and status registers. The 10BASE-T part of SEPHY contains a Manchester encoder and a shaping filter on transmission and a Manchester decoder on reception. The device operates at 100MHz in this mode so that 10 samples are available per symbol, which facilitates the receiver implementation. In 100BASE-TX mode, the device operates a 125MHz so that only one sample is taken per symbol. The 100BASE-TX transmit path includes a 4 to 5 bit mapping followed by a scrambler and an MLT3 encoder. The receiver for 100BASE-TX is by far the most complex block of the device and includes, a programmable gain amplifier, an adaptive feed forward equalizer, clock recovery and baseline wander functions, an MLT3 decoder and a descrambler. The Analog Front End (AFE) contains a Digital to Analog Converter (DAC) and a shaping filter on transmission. On reception, it has a Programmable Gain Amplifier (PGA) to compensate cable attenuation followed by an Anti-Aliasing Filter (AAF) and an Analog to Digital Converter (ADC). A Delay Locked Loop is also used to adjust the clock of the ADC to that of the remote transmitter and a small DAC is used to compensate the Base Line Wander (BLW). These last two blocks are only needed in 100BASE-TX mode. The common block generates the clock and reset signals for the rest of the blocks. To that end it has a Phase Locked Loop (PLL) that can generate a 100MHz or a 125MHz clock depending on the mode selected (10BASE-T or 100BASE-TX). The common block also contains the Management Data Input Output (MDIO) interface defined in the standard to configure the transceiver and check its status. 3. Transceiver Implementation The architecture described in the previous section has been implemented in Microchip´s 150 nm SOI technology targeting a 64 pin CQFP encapsulation. The device has a total area of 18.5 mm2 and an estimated power consumption of 270 mW in 10BASE-T mode and of 635mW in 100BASE-TX mode. The digital part occupies most of the area with a total of around 80kgates. In more detail, over 75% of the area is digital and the rest is analog. On the digital part, the largest block is the adaptive equalizer that accounts for more than two thirds of the digital area. On the analog side, the largest block is the PLL. 4. Conclusions This paper has presented the prototype of SEPHY, the first European space grade 10/100 Ethernet transceiver. The device has been manufactured with Microchip 150nm technology and is designed to withstand radiation so that it can be used in most space applications. Electrical and radiation tests on silicon are expected for August 2018. System tests will be performed in September 2018. **Acknowledgements** This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No.64024. [1]: http://Z:%5C2015%5C15101-SEPHY_H2020%5C15101-Documentaci%C3%B3n%20de%20Proveedores%5CUAN%5CPapers%5CAMICSA%202018

Speaker: Mr Jesús F. López-Soto (Arquimea S.L.U.)

Paper SEPHY_AMICSA2018.pdf

14:00 → 16:00 Poster: Evaluation and Qualification

14:00 → 16:00 Poster: Radiation Testing and Mitigation

14:00 Heavy Ion Test Results of Different Analog to Digital Converters

This paper presents the results of heavy-ion induced single event effect (SEE) tests, performed on analog to digital converters (ADC), which are candidates for usage in spacecraft electronics. The experimental data was obtained at Roscosmos Test Facilities during test campaigns in 2017.

Speaker: Mr Sergei Iakovlev (Branch of JSC “URSC” - “ISDE”)

Paper Heavy_Ion_Test_Results_of_A-D_Converters.pdf

14:00 Radiation Tolerant Stochastic Fourier-Transformation Implementation

The Fourier-Transformation is used in numerous applications. The Fast Fourier-Transform (FFT) algorithm allows an efficient hardware implementation. For space applications, radiation (R) is one of the most significant factors to be taken into account, when the reliability of electronic equipment is in the focus. Long-term usage and large temperature variations are present for electronic devices in satellites as well. On circuit level for terrestrial applications the keyword summing up these effects is PVTA, which is the short form for process variations (P), supply voltage variations (V), temperature (T) and aging (A). All these effects (PVTAR) cause bit errors in digital circuits leading to wrong calculations. Since charged particles have the major influence on the accuracy, we will limit ourselves to Single Event Effects (SEE) in the following. Within a fixed-point (FI) representation, such errors have of course the highest impact on the MSB. On the contrary, stochastic computation (SxC) uses bit streams and stores the information in the frequency of a logical 1 or the ratio of logical 1's to 0's. This way all bits have the identical significance and the outlined impacts are expected to have less severe effects on the reliable calculation. This will be demonstrated for the Fourier-Transform. Considering two bit flips, the first one from a 0 to a 1 and the second one vice versa, the actual impact on the FI representation depends on the positions in the digital word, while for the SxC case the errors impacts cancel each other out. A simulation environment is set up to compare both approaches: on the one hand a double precision, scaled fixed-point FFT and on the other hand a stochastic DFT using the two line bipolar representation. Evaluations on the performance are based on the accuracy of the calculated spectrums for a given complex input signal with 64 samples. The FI representation uses 64 bits on the real and 64 bits on the imaginary part for each sample. The SxC system encodes the input signal with four streams (real / imaginary + positive / negative) with 1024 bits each. Both systems are analyzed for different scenarios. Each sample in each case is calculated 100 times and its respective mean is used to compare the systems with each other. In the first place, when no PVTAR effects are present, the FI system can show its higher accuracy and precision compared to the SxC approach; both setups are related to the built in FFT function. The absolute error of the mean of the FI setup is in the order of $10^{-16}$. This value needs to be compared to the order of $10^{-3}$, which was achieved for the SXC approach. Both results prove the afore mentioned expectations and offer good spectral analysis, high accuracy and good precision. Assuming additional scenarios with increased linear energy transfer (LET), process variations, temperature of e.g. 120°C and a supply voltage of 0.8V both setups will need to show its performance. The normalized mean squared error (NMSE) and the signal to noise ratio (SNR) show the PVTAR tolerant characteristic of the SxC approach. Secondly, the aspect of computational complexity is discussed. The stochastic approach has an overall factor of 32 more bits to be stored and processed for calculations. One has to take into account, the more bits are used, the more errors will be present. It is known, that a common N point FFT requires operations of order $O(N log_2 N)$. In more detail the stochastic approach can be reduced to 16N parallel multiplications (logical AND gates) and one large adder (multiplexer with 16 inputs).

Speaker: Mr Kris Niederkleine (Institute of Electrodynamics and Microelectronics - Universität Bremen)

14:00 The First SEE Tests Campaign in Turkey at the METU Defocusing Beamline Preliminary Setup

The preliminary setup of the METU Defocusing Beamline was commissioned in December 2017. This beamline, which is at the Turkish Atomic Energy Agency (TAEA) Saraykoy Nuclear Research and Training Center (SANAEM), follows the R&D beamline at the 15-30 MeV proton cyclotron of Proton Accelerator Facility (PAF). The preliminary setup, with two quadrupole magnets provides an irradiation area of 4x6cm with 15% radiation dose uniformity, with a flux of 3.8x10^9 p/cm/s^2. The final setup which will be constructed and commissioned at the end of 2018, will have a adjustable collimator and 3 quadropole magnets, providing users with an irradiation area conforming to the ESA-ESCC 25100 standard, with 10% radiation dose uniformity and a flux menu selectable between 10^6-10^10. The first SEE tests at the preliminary setup were performed with a collaboration of TUBITAK Space Institute. A test card was designed around two units of buffers and the readout was performed using an oscilloscope with frame capture. Two rounds of 25 second DAQ windows were acquired. In this talk, we will first present the METU DBL project and then the results of the SEE tests performed at this new facility.

Speaker: Mr Mehmet Serdar Aydin (METU)

Paper The_First_SEE_Test_Campaign_in_Turkey_at_the_METU_Defocusing_Beamline_Preliminary_Setup.pdf The_First_SEE_Test_Campaign_in_Turkey_at_the_METU_Defocusing_Beamline_Preliminary_Setup_v1.doc

14:00 → 16:00 Poster: Space Applications

Convener: Mr David Levacq (ESA)

14:00 A rad-hard signal conditioning ASIC for space grade transducers

European Sensor Systems S.A is a global developer and manufacturer of high quality sensors based on MEMS. In the course of an ESA activity, titled “Space Qualified Family of MEMS Pressure Modules for Satellite Applications”, European Sensor Systems S.A is developing a custom radiation-hardened capacitive sensor signal conditioning ASIC for interfacing with the MEMS pressure sensors. The ASIC is built using X-FAB XH018 Process Design Kit, a 0.18 micron Modular Mixed Signal High-Voltage CMOS Technology. This paper presents the approach followed to solve the issues identified during the test campaign of the first revision and were mainly related to irradiation effects at the output stage of the ASIC as well as early characterization results. To start with, the ASIC is capable of interfacing both single and differential sensor architectures. The range of the full-scale input capacitance changes up to ±5.6pF, with a base capacitance of up to 40pF in order to cover the application requirements for pressure ranges of 7, 22, 150, 310 bara. Sensor capacitance variations can be compensated by an on-chip trimmable capacitor bank. The Capacitance-to-Digital Converter combines the Capacitance-to-Voltage converter with a second order ΣΔ modulator and a decimation filter to produce a high resolution output with a programmable update rate. It also incorporates a temperature sensor. In order to reduce the effect of low frequency noise and mitigate the problem of amplifier offset due to TID irradiation, a circuit-level approach has been used at the sensitive core blocks. An operational amplifier with chopper stabilization has been used for the capacitance-to-voltage converter. Using this technique the offset and 1/f flicker noise are modulated away from DC. For the ΣΔ switched-capacitor modulator, the correlated double sampling technique has been used for the amplifier of the integrator, which is the most critical element of the modulator. The ASIC, which has a current consumption of approximately 6 mA, is powered by the space-qualified version of LM117 component, which is a radiation tolerant three-terminal adjustable output linear regulator providing 5.7V output, the analog and digital cores operate at 3.3V internally while the I/O is performed at 5.7V level. The device provides two 32-bit digital outputs accessible by the serial interface: A non-calibrated capacitive measurement output and a temperature output as well as an analog output with 10-bit resolution. At system level, the requirement is to provide 0V at zero pressure and 5V output at maximum applied pressure (105% of max pressure range). At the first ASIC revision, a level translator from 3.3V to 5.7V was incorporated to up-convert the PWM output and the RC filtering was performed externally. The output stage of the level-converter was using an inverter with high-voltage transistors. Due to total dose irradiation the off-resistance of the high voltage NMOS transistor was decreasing giving rise to a higher current. The increased sink current was creating a smaller output swing at the PWM output, thus affecting the output voltage. At the second ASIC revision, the PWM output scheme is redesigned. The digital PWM output is filtered internally and the filtered output is applied to a closed-loop amplification stage. In this configuration the output voltage is merely set by the ratio of the input and feedback resistors. In order to address the problem of SEE the Triple Module Redundancy method with voting has been adopted. This technique has been applied at the level of digital synthesis. The TMR technique has been applied to all flip-flops of the digital part. In order to address the problem of SEL in the digital part, a library of custom digital cells has been designed and characterized in house to enhance radiation tolerance. It is a 3.3V junction isolated, low power library and contains combinational, sequential and special cells. In the analog part, all PMOS devices have been enclosed by N-type guard rings and all the NMOS devices have been enclosed by P-type guard rings. The size of the ASIC is 3mm x 2 mm and has been manufactured and tested. After electrical characterization the irradiation campaign took place. The TID experiment was performed using ten DUTs at the ESTEC Co-60 Facility up to 100 Krad. The DUTs electrical parameters were measured before irradiation, then they were subjected to 6 pre-specified irradiation dose steps and critical electrical parameters were measured after each step to investigate potential variations in performance. Afterwards, two annealing steps followed. The electrical parameters of the DUTs were measured after 24h and 168h of operation at room temperature. The experiment then concluded with an accelerated ageing test. Preliminary TID results have shown that the digital outputs are not affected by TID. As far as the analog output is concerned, a small error is related to the dependency of an internal bias voltage to the internal voltage generated by a bandgap reference circuit. This is because of the bipolar transistors, which suffer from radiation–induced leakage current. The holes trapped in the thick Shallow Trench Isolation (STI) oxide lead to an increase in the leakage current, which occurs at the interface between STI oxide and p-doped regions. The ASIC has also been tested for SEL/SET in the UCL cyclotron accelerator facility at worst case conditions (maximum voltage supply, 85 °C). The ASIC exhibited immunity when exposed to irradiation heavy ions C, Ne, Ar, Ni, Kr, Xe. Finally, the ASIC has been exposed to a Displacement Damage at UCL facility exhibiting robustness after exposure to 62 MeV proton fluence of 2E11 #/cm2 with a maximum flux of 2E8 #/cm2-s. Currently, the ASIC is being used to create engineering models of the space transmitter, which will be calibrated and then undergo mechanical and stress tests. In conclusion, robustness of the ASIC to Single Event Effects (SEL and SEU) has been proven through the irradiation campaign due to the appropriate design approach at different levels (physical, architectural). In order to minimize TID effects and further enhance radiation tolerance, an optimization of the bandgap reference generator using Enclosed Layout Transistor (ELT) could be supportive.

Speakers: Mr Dimitris Mitrovgenis (Senior IC Designer), Mr Theodoros Athanasopoulos (Technical Director)

14:00 Multi-Channel Preamplifier IC for IR-Sensor and FPA Readout

We present the IDE1060, an integrated circuit (IC) with 34 preamplifiers for reading out infrared (IR) sensors and focal plane imaging arrays (FPA). We designed the circuit under contract with the European Southern Observatory (ESO) where the device shall be used with typical large format astronomical IR sensors, e.g., Raytheon Aquarius and Teledyne HAWAII-2RG. The IDE1060 is intended to replace the fast readout amplifiers described in Ref. [1]. The circuit is designed for extreme operational environmental conditions: cryogenic to room temperature, latch-up immunity and high energy threshold for single event upsets from ionizing radiation. Based on the design methods we expect the circuit to be suitable for space-borne astronomical instruments as well. The device is manufactured in Q1 2018 and characterization is planned for the remainder of the year.

Speaker: Mr Jörg Ackermann (Integrated Detector Electronics AS)

15:00 → 16:00 Coffee

16:00 → 17:15 Custom Cell-, Circuit-, and System Design: (3/3)

Custom cell-, circuit-, and system design of ICs for space applications Full custom digital, analogue, or mixed-signal: Front-end, Signal processing, Data converters, Receivers and transmitters, Drivers, or other.

Convener: Mrs Florence Malou (CNES)

16:00 Prototype of a multi-mode C-Band capable 12-bit 1.5/3/6 GSps Quad ADC in flip-chip non-hermetic technology

Teledyne e2v has developed a new ADC to meet the high dynamic range as well as channel integration requirements of telecommunications payloads. It is a quad channel single core 12bit 1.5 GSPS designed by Teledyne e2v on ST Microelectronics BiCMOS9 technology which features 0.13µm CMOS and SiGeC NPN HBT bipolar technology (Ft/Fmax = 166/175GHz). The built-in Cross Point Switch (CPS) allows a multi-mode operation with the possibility to interleave the four independent cores in order to reach higher sampling rates. In 4-channel operation mode, the four cores can sample, in phase, four independent inputs. In 2-channel operating mode, the cores are interleaved by 2 in order to reach 3 GSps sampling rate on each one of two inputs. In 1-channel operating mode, a single input is propagated to each one of the four cores which are interleaved by 4 in order to reach a sampling rate of 6 GSps. The -3dB input bandwidth is more than 5 GHz in order to be able to directly sample signals in the C-band (4-8 GHz). This high flexibility enables the access to microwave-frequency signals with up to 3 GHz of instantaneous bandwidth. It also enables the qualification of a single component which is capable to meet a variety of application needs from single to multi-channels, from baseband to more than 5 GHz of input bandwidth. The device is built in a non-hermetic flip-chip package using HiTCE (High Coefficient of Thermal Expansion) glass ceramic material in order to reach optimized RF performance and higher pin density. The new high reliability European flip-chip assembly line deployed by Teledyne e2v is being used for this device. Teledyne e2v is a leader of the flip-chip assembly Working Group which has introduced flip-chip assembly in the ESCC Generic Specification n°9000 in 2016. The paper will develop the following aspects: Target noise power ratio performance in multiple Nyquist zones Cross talk isolation in excess of 70dB at 2.4GHz Chosen ADC architecture, including built-in Cross-Point Switch for multimode operation Introduction of chained ADC synchronization for antenna arrays System benefits of C-Band high dynamic range digitization Mitigation of radiation effects on ST Microelectronics BiCMOS9 technology. Choice of package technology: RF performance and 2nd level reliability Challenges of Flip-Chip assembly at space level.

Speaker: Dr Romain PILARD (Teledyne e2v)

Paper AMICSA2018_Pilard_Multi_Mode_Quad_ADC.pdf

Slides Prototype_of_a_Multi-Mode_C-band_Capable_ADC.pptx

16:25 Atom-Switch FPGA for IoT Sensing System Application

The Internet of Things (IoT) has been envisioned as a fundamental infrastructure that will bring about useful information and knowledge resulting in efficiency and growth in industry and improved comfort and safety in human life. Sensors, networks, and information technology (IT) are designated as key technology elements to make IoT a practical knowledge framework. IoT is to be used for supporting so-called lifeline as energy supply, water works, traffic control, logistics, broadcasting, and telecommunication. Everything is to be connected through Machine to Machine (M2M) network anytime and anywhere to realize the IoT framework. Space systems, such as satellites, can be identified as sensor nodes and relay nodes among IoT applications. It is integrated with ground systems, and wide range of collected information must be transmitted through the limited transmission capacity of existing network. Thus, it is essential to reduce the data size by computationally intensive algorithms including data compression, data prediction, adaptive sampling, and so on. Field programmable gate arrays (FPGAs) with high performance computation are suitable for this purpose. Especially, a single-event-effect (SEE) free FPGA is the most desirable device because the demanding characteristics on satellites is a continuous operation in harsh environment with background radiation in orbit. Low power consumption is another demanding characteristics for realizing less heat dissipation indispensable to space applications operating in exoatmosphere. We have developed an atom-switch based FPGA with radiation hardened characteristics. Atom switch provides rewritable capability for FPGAs without static random access memory (SRAM) or electrically erasable programmable read-only memory (EEPROM) to store circuit configurations. The atom switch functions as routing switch and memory bit in look-up table (LUT). The atom switch has a durability against radiation. This results in mitigating SEE in circuit configuration of FPGA. Memory patrol and memory scrubbing functions are not required for the atom-switch FPGA, and that eliminates external peripheral devices used with conventional rewritable FPGAs. Atom switch is a resistance-change type nonvolatile switch. The novel switch is composed of the solid electrolyte sandwiched between Pt and Cu electrodes. When a positive voltage is applied to Cu electrode, Cu is ionized and precipitated at Pt electrode, and then a conducting metal bridge is formed between Cu and Pt electrodes. The conductance of the switch changes to high (or ON state). When a negative voltage is applied to the ON-state atom switch, the metal bridge is broken and dissolved into the solid electrolyte and the switch turns off. The programming cycles is up to 1,000. The switch’s resistance value is maintained even when the power supply is turned off, resulting in nonvolatile FPGA. The fabricated atom-switch FPGA includes a 40 x 40 logic cell array, each of which consists of a switch block and a logic block including 4x 4-input LUTs. The 4.38-Mb atom switches are integrated between metals 4 and 5 of Cu interconnect using 40-nm CMOS technology. To achieve a high OFF state reliability, two atom switches are serially connected with opposite direction in each element. Two atom switches are programmed by using the cell transistor connected to the middle node. This switch is named as a complementary atom switch (CAS), since the voltage stress is shared by two atom switches complementarily. Small area and small capacitance (~0.14fF) of CAS contributes to low power consumption and high speed of FPGA. Its non-volatility also allows an immediate wake-up/sleep operation without re-loading the configuration data, and saves the standby power effectively. We compared the performance of the atom-switch FPGA with the commercial SRAM-based FPGA, which was a low-power one (iCE40) for mobile applications by Lattice Corp. The benchmark circuit of 16-bit Arithmetic Logic Unit (ALU) was mapped on both FPGAs. The atom-switch FPGA operated at 3.8 times faster clock frequency over the conventional one. The dynamic and active power consumptions of the atom switch FPGA were reduced by 67% and 39%, respectively. These improvements are mainly originated from small capacitance of atom switch and smaller logic-cell size, which is a half of the conventional one at same technology node of 40nm. Radiation resistance of atom switch was evaluated by using a heavy ion cocktail beam. For this evaluation, array of 128k-bit atom switches or atom-switch FPGA were used. The array of atom switches were exposed by Xe and Kr ions. Linear energy transfers (LETs) of Xe and Kr were estimated to be 68.9 and 40.3 MeV/(mg/cm2) at the chip surface, respectively. During the irradiation, we observed no SEE, showing that SEE cross section is at least 100 times lower than that of NAND flash. The atom-switch FPGA will be evaluated in orbit via the innovative satellite technology demonstration program of JAXA in FY2018. During a whole year, the full-HD image will be compressed in the atom-switch FPGA and transmitted to ground stations.

Speaker: Dr Toshitsugu Sakamoto (NEC Corporation)

Slides 20180619_SAKAMOTO_AMICSA2018.pdf

16:50 Robust CMOS time-based sensor interfaces for space applications

The harsh environment of space mission applications is at the same time a growing field and a challenging playground for electronic sensor systems. The need of accurate and reliable information about several parameters such as structure sanity, turbine combustion and fuel tank state, among many others, requires sensor systems to be placed *in situ*. Thus, robust, reliable and accurate sensing systems are required to operate in hostile environments under extreme temperature, pressure, humidity, vibration and radiation conditions. Several harsh-environment-compatible features have already been demonstrated using the BBPLL-based CMOS sensor interface architecture for both capacitive and resistive sensors. The main property of this time-based architecture is the robustness provided by the direct sensor-to-digital conversion, by means of the time-domain representation of the sensor data. Since the signal does not need to be amplified before digitization, area- and power-consuming analog blocks and their nonideal effects are bypassed. Additionally, its oversampling operation provides enough redundancy to filter out in the digital domain corrupted data produced by analog transient effects such as single-event radiation effects. Another feature is the highly-digital implementation, compatible with digitally-assisted techniques such as time-based signal chopping and differential-path tuning which can improve the resolution and accuracy performance of the system by reducing the effect of DC and low-frequency perturbations. These techniques can be configured to implement simple built-in self-test strategies that can provide information about the state of the circuit and feed it back for compensation. In such way, smart system-level operation can be achieved by driving capabilities at local level, for example in the case of wireless sensor networks. This paper presents an overview of the robustness properties of time-based sensor interfaces demonstrated until now in CMOS technologies, which indicate a good compatibility with space applications. Furthermore, the presented demonstrators constitute a good example on how CMOS technologies are used as a low-cost prototyping platform to explore space solutions to be further implemented in more expensive technologies used in space applications. Two study cases are discussed. The first demonstrator is a BBPLL-based capacitive sensor interface which can achieve 14-bit resolution. The interface uses time-domain chopping as the main source of compensation between the VCOs mismatch and low-frequency noise. It shows high linearity operation, which simplifies calibration by reducing the number of calibration data points needed. The second interface is a fully-differential BBPLL-based resistive-bridge sensor interface. It provides a very high drift resilience by combining different digitally-assisted techniques. A simple online monitoring technique allows to compensate for sources of drift other than temperature, such as package strain variations and circuit component degradation. Thus, this interface is suited for very harsh environments. The target temperatures in this work, even if far from the maximum required values for space applications, demonstrate the validity of the subjacent principles. The examples discussed have medium-to-high resolution, consume low power and a have a small footprint. This implies low-weight implementations since low volumes are needed for the chip and the batteries. This work constitutes a step towards robust, accurate, light/compact and smart wireless sensor systems which can collect and process high fidelity data locally in nowadays’ space missions.

Speaker: Mr Jorge Marin (KU Leuven)

Paper AMICSA2018_Robust-TBSI-for-space_v3p2_28052018.doc

Slides AMICSA2018_JMARIN_KUL_V1P5FINAL_19062018.pptx

19:00 → 21:00 AMICSA: Conference Dinner

Wednesday, 20 June

09:00 → 09:45 Keynote Speach: (2/2)

09:00 Perspectives for Disruptive GaN Power Device Technology

Today, GaN-on-Si is accepted as a break-through power electronics technology. The favorable materials characteristics and the enhancement mode lateral HEMT device architecture have led to disruptive device performance. Issues with trapping effects and reliability that plagued early versions of the technology have been addressed and first products are in the market. While we will see through further evolutionary improvements the maturity of today’s GaN-on-Si technology further increase with fast pace, research is focused on substrate technology, novel device architectures, application specific customization and higher levels of integration. To unlock the full potential of the fast switching power devices, monolithic integration of a half-bridge, co-integration of the GaN drivers, and free-wheeling diodes offer a way to reduce parasitic inductances, while on-chip temperature sensors and protection circuits increase the robustness. Such power GaN-IC’s pave the way for unprecedented compact high-end power systems.

Speaker: Stefaan Decoutere (IMEC)

Slides Perspectives_for_disruptive_GaN_power_device_technology_V2.pptx

09:45 → 11:00 Radiation Hardened Technologies: (1/3)

Radiation-hardened technologies for analogue and mixed-signal ICs

Convener: Dr Constantin Papadas (ISD SA)

09:45 Microchip ATMX150RHA Rad-Hard CMOS 150nm cell-based ASIC family Radiation Characterization Test Report Total Dose (TID) and Single Event Effects (SEE)

Leader of Microcontroller, Mixed-Signal and ASICs solutions since 30 years, Microchip has developed a large ASICs offer based on 0.8µm to 150nm technologies. The ATMX150RHA ASICs offer is based on 150nm SOI proprietary technology with a Rad-Hard process. This technology is qualified through ESCC and DLA standards for 22Mgates 1.8V & 3.3V digital circuits. Mixed-signal challenge has been addressed through a fully electrical and radiation characterization of elementary devices, using different test chips: Standard Evaluation Circuit (SEC) & Analog Test Vehicle dedicated to: - Digital blocks: hardened standard-cells, hardened Flip-Flops & compiled memories - Analog IPs: Voltage regulator & reference, clock synthesizer & signal conditioning. A large choice of devices are available as MOS 1.8V, 3.3V, 5V, 15V and LDMOS 25V&45V, developed and simulated in the range of -55°C to 145°C junction temperature. This paper presents the current radiation overview of the ATMX150RHA devices contained in the PDK. Are covered the following items: Single Event Latch-up (SEL), Total Ionizing Dose (TID), Single Event Gate Rupture (SEGR) & Single Event Burn-out (SEB) for HV devices. A focus is done on Single Event Transient (SET) & Single Event Upset (SEU). SEL The ATMX150RHA technology, using a Partially Depleted SOI is naturally SEL immune by implementation of Deep-trench capability. Nevertheless, Microchip has developed a high density processed solution for digital and compiled memories to keep SEL immunity without use of Deep Trenches. High radiation SEL capability has been demonstrated with a SEL LET threshold > 60 MeV.cm2/mg. TID The ATMX150RHA technology is RHA level R for low voltage devices. High radiation TID capability has been demonstrated with: - TID threshold > 100 krad(Si) for 1.8V to 3.3V devices. - TID threshold between 30 krad(Si) and 50 krad(Si) for other devices and some IPs. Post rad TID spice models are available for LDMOS. SEGR&SEB Post Rad SOA are introduced for LDMOS devices after SEGR and SEB characterization. SET/SEU Single Error Rate are available for ATMX150RHA standard cells, memories and some IPs after characterization of SET/SEU effects. The high Single Event Transient (SET) soft error rate of integrated technologies becomes a major concern. It is the reason why the SET pulse width measurements or calculations are necessary to determinate the SET circuit sensitivity and optimize the radiation hardening. Thus, the measuring and modeling of the widths of transient voltage pulses are critical for the prediction and mitigation of soft errors. The RAdiation Prediction TOols on Rhbd (RAPTOR) is a platform able to model the SET pulse width and assess the sensitivity of circuits to SET/SEU by considering the topology of the layout, the power supply, the logical states, the logic masking, the narrowing and/or broadening of the SET pulse widths. This platform is a suite of tools including the software MUSCA developed and supported by the ONERA, and a list of MICROCHIP® proprietary tools developed in the framework of this project. The challenge was to integrate MUSCA® into a MICROCHIP® design flow and propose a user-friendly platform usable by all the designers. The tool has been successfully validated on standard cells (combinatory cells and sequential), and complex circuits such as clock trees. The platform is now integrated in the design flow, and each new digital IP or standard Cells is assessed to SET/SEU by using RAPTOR. The adding value of RAPTOR is its ability to assess easily, and in a short time the radiation sensitivity of a circuit, IP or standard cell. The effort deployed on the user-friendly interface is a plus. Also, RAPTOR is a key tool to improve the customer support on the radiation hardening.

Speaker: Mr eric leduc (1967)

Paper ATMX150RHA_radiation_characterization_summary.rev1.0.pdf

Slides Radiation_Charac_AMICSA_r1.0.pdf

10:10 DARE180U platform improvements in release 5.6

DARE180U, formerly named DARE180, is a mixed-signal ASIC design platform intended for radiation hardened applications up to 1 Mrad implemented in the commercial UMC L180 MM/RF 1.8V/3.3V, Single Poly 6 Metal (1P6M), P-Sub/Twin-Well CMOS technology. Over the years, DARE180U has been adopted by many partners around the world and it has recently obtained maximum TLR-9 status with chips launched in commercial planetary missions. Release 5.6 is a major step in the DARE180U solution as it brings together extensive knowledge acquired in the past years from several application designs and test chips. This paper discusses the updates in this release which includes general improvements made to the platform as well as new additions and enhancements on existing libraries and IP. General improvements include the support to full-custom black-box design and the use of a new ELT simulation model that has been fine-tuned using comprehensive test results from the DARE+ project supported by the European Space Agency. DARE180U CORE library has been fully reviewed to optimize sensitive area of critical nodes and to improve electrical behavior around ELTs. More efficient layout techniques have also been employed to reduce area in most cells and to enable better top-level routing. As well, characterization data using the new fine-tuned ELT models has been generated to deliver more accurate timing results. I/O libraries have been completely rearranged with all digital and analog I/O cells being included in a single library whereas bond pad cells are provided in a separate library. The new I/O cell library has been largely extended with new analog cells, breakers and supply cells that enables different implementations of 1.8V and 3.3V mixed-signal domains in a single I/O ring. As well, several modifications have been done on layouts to improve ESD behavior and electromigration. The new bond pad cell library includes an entirely new set of structures featuring several pad opening sizes for different pitch requirements as well as special double bond pad cells to be used with DARE180U-specific IP. DARE180U IP, such as LVDS and PLL, have also been updated to attend new requirements and to fix existing issues reported in previous application chips. On top of these, new IP implemented at imec have been added to the platform such as ADC, DAC, bandgap, LDO and ring oscillators. In this release, the DARE180U SRAM compiler has been revised to fix known bugs and to deliver more accurate characterization data based on new ELT models. This compiler features the implementation of both single-port and dual-port SRAM blocks with possible sizes ranging from 256 bits to 256 Kbits. All generated instances are in line with the TID specifications of the DARE180U libraries and MBU insensitivity can be achieved by specifying proper bit interleaving in the compiler and employing external error detection and correction circuits.

Speaker: Mr Giancarlo Franciscatto (imec)

Slides AMICSA2018_DARE180U_5v6_presentation.pptx

10:35 The Design Against Radiation Effects (DARE) design platform for TSMC 65nm process.

In the last decades the evolution of the technologies for space ASIC and chip production is bringing a high level of miniaturization, giving benefits in terms of less power consumption, less mass, less volume, reduced number of components on the boards, better testability, higher performances and reliability. Newest space technologies (optical and RF communications) as well as miniature CubeSats and communication satellites are demanding more and more performance from electronic components. At the same time, satellites’ reliability and lifetime requirements are still requesting for TID and SEE radiation hardness. Space System Designers are always looking for the best integration, area, power, performance, mass, volume, radiation hardness and cost tradeoffs. Hence, there is always a demand to go for not only nodes with more capabilities, but also to more advanced nodes, for they bring new capabilities to the playing field. As the lead time to access new technologies for the development of ASICs for Space applications is several years, and the long-term availability is limited by the technology lifetime, it is important to give system designers for Space applications access to these technologies as early as possible. DARE65T is a new radiation hardened (RH) high-performance system-on-a-chip (SoC) design platform including mixed-signal and analogue building blocks. It is built on the commercial TSMC 65nm LP 1.2V/2.5V CMOS technology. The DARE65T incorporates a set of standard and IO cell libraries, LVDS and SSTL cell libraries, memory and analogue IPs. The DARE65T development is based on common radiation design rules, which are implemented in an analog design kit (ADK). This approach facilitates also full custom radiation aware analogue design. DARE65T meats the main performance requirements of Space equipment designers. The paper is focusing first on the irradiation test results of 65nm CMOS structures. This is significant step to define the design platform basis concerning radiation effects (TID, SEL, SEU, SET) mitigation methods. Second paper section is general overview of ADK development. The ADK incorporates and provides automatic checks of all chosen design rules, designers must follow in order to create RH ASICs. Another important point when doing radiation hardening by design for mixed-signal and analog blocks is simulation of SET events. ADK also provides the environment for such simulations. Standard cell and IO cell library is a next step of platform development and thus next paper section. The paper gives an overview of standard cell layout template, used design methods against SEL and SEU. The DARE65T_CORE library has several types of cells allowing for designers to choose the right optimum between SEU/SET hardness level and area. As it was mentioned in the introduction the Space designs are demanding more and more performance. The ASIC performance means not just a clock frequency, but also high-speed interfaces. Among classical requirements for LVDS IO cells in order to build SpaceWire interface links, there are new requests for DDR interface and high-performance link, for example RapidIO or PCIe or JESD204. DARE65T platform supports such needs providing set of LVDS and SSTL IO cells. The relevant section of the paper gives detailed overview of such platform capability. Last paper section represents the analogue IP and memory IP which are the significant building blocks of future ASICs intended for space application. It also describes the main functional features and electrical parameters. DARE65 libraries are reliable design platform for competitive high-performance radiation hardened ASICs.

Speaker: Mr Michael Kakoulin (IMEC)

Slides DARE65_ESA.pptx

11:00 → 11:20 Coffee

11:20 → 12:35 Radiation Hardened Technologies: (2/3)

Radiation-hardened technologies for analogue and mixed-signal ICs

Convener: Mr Franco Bigongiari (SITAEL S.p.A:)

11:20 Overview of ST Space Qualification in 28nm-FDSOI

The good intrinsic radiation resilience of the 28nm-FDSOI technology was demonstrated and reported by ST in 2014. The full space compliance of the ST industrial design platform has additionally required a wide deployment in terms of proprietary radiation modeling, design mitigation and extensive testing against protons, heavy ions and gamma rays. This overview presents 100 new space IPs in 28nm-FDSOI (std cells, memories, serdes, converters, PLLs, analog IPs, sensors) whose space qualifications are being completed by ST thru 25 existing testchips. Last, but not least, the concurrent design of new best-in-class space SoC (ARM-R52, FPGA) is also illustrated in ST 28nm-FDSOI.

Speaker: Dr Gilles Gasiot (ST Radiation Team Crolles)

11:45 ATMX150RHA Circuit Design Platform

Microchip Technology Inc. is a leading provider of microcontroller and analog semiconductors, providing 150nm SOI technology (ATMX150RHA) for space product design. We manage full space product supply chain till qualified packaged products according to agencies standards, including foundry and ASIC design services. Building on ATC18RHA heritage, the ATMX150RHA design platform extend possibilities from digital to analog and mixed signal circuit design. To ease SoC design, Microchip provide qualified radiation hardened libraries of IOs, standard cells and analog IPs. Qualified domain extension to analog macros, use a strategy based on enhanced Standard Evaluation Circuit and dedicated test vehicle. Our enhanced Standard Evaluation Circuit contains digital requirements to qualify our technology up to 22M gates, analog monitoring cells, and a set of representative analog IPs. Our test vehicles are used to characterize analog IPs in a standalone mode, for electrical characteristics, radiation robustness and life time. A first set of IPs have been design and successfully qualified. These IPs are: - a linear voltage regulator, including power monitoring features - an analog multiplexer - an internal oscillator - a bandgap voltage reference We will present our results. In order to support analog or digital on top design flows, we provide packages containing libraries (IOs, standard cells and IPs). For digital design flow, physical, timing and behavioral models are provided. For analog design flow, we provide IOs and standard layouts and schematics. Regarding IPs, a black box layout and encrypted spice netlist are provided to allow integration and simulation

Speaker: Mr Erwann BERLIVET (Atmel/Microchip)

Paper ATMX150RHA_Circuit_Design_Platform.doc

Slides AMICSA_ATMX150RHA_Circuit_Design_Platform.pptx

12:10 DARE SET Simulation Flow Integrated in Virtuoso ADE L/XL Design Environment

One of the important steps when doing radiation hardening by design for mixed-signal and analog blocks is simulation of SET events. It is needed to find the SET sensitive nodes in a design and then adapt the design to bring the SET hardness in compliance with the specification. In order for an analog designer to do this efficiently the tools used should be integrated in the normal analog design flow. It should be flexible enough to screen for sensitive nodes in a design and later on focus on certain nodes. In analog design the timing of an event is important as a strike often only generates a non-compliant SET on the output when the circuit is in a certain state or transition. The timing may be dependent on the simulation corner and ideally the testbench should not need to be changed for this dependence. Additionally it should be avoided that a certain circuit has to be adapted to be able to inject an SET pulse in any node in its hierarchy. Up to now for DARE development at imec a SET_STRIKER cell combined with a deepprobe cell was used. The SET_STRIKER is a model for the SET pulse generated by a single strike of a particle. The purpose of the deepprobe – included in the latest releases of analogLib included in Virtuoso IC – is to allow to inject in any node in the hierarchy of the circuit without the need of adaptions in the circuit. Alternatively, an ocean script is used to inject SET pulses in all nodes in a design. With the extensive use of these tools possible improvements were indentified: * The single strike generated by one SET_STRIKER meant that for each event that one wanted to include in the simulation a separate instance had to be included in the testbench and the timing between the events had to be set manually. Each of the SET_STRIKERs had to be accompanied with its own deepprobe to inject in the right location. If one wants to do a simulation on only a subset of the nodes all the unwanted ones has to be disabled manually. * The deepprobe only connected to one node so it was assumed that the injection always happened with the other end of the SET_STRIKER connected to either the ground or the supply of the circuit. This is most of the time the case as most of the time the bulk of a transistor is connected to one of these nets. When this is not the case two deepprobes should be used but that may be overlooked when setting up the test bench. * The ocean script is mainly used for checking of standard cells and does not have the right capability to properly time the events as needed for analog radiation hardening by design and is not integrated in the analog design flow. In the DARE65 project (contract no. 4000117214/16/NL/LF) then the SET simulation flow was improved based on the identified shortcomings: * SET_STRIKER was extended with a SET_STRIKER_PERIOD and a SET_STRIKER_TRIG cell. These two cells allow to generate several SET pulses. The first cell generates events with a periodic repetition and the second one events triggered by an input signal. * A dual deepprobe was made that connects to two nodes in the circuits. It uses a list of node pairs and can switch between the pairs during the simulation. Again two variants are available, one that switches periodically and one that switches triggered by external signal. * A support window is available to get a list of all sensitive nodes in the circuit under test and select a subset of the nodes for simulation. This set can then be saved. It also allows to highlight the nets and nodes of the selected pairs. * A second support window is available that allow to look up the nodes to which an SET pulse was injected in the circuit under test. With these improvements implemented the analog designer now has a flexible tool set that allows to simulate all needed events with a single instance of a deepprobe and an SET pulse generator with the needed flexibility and efficiency to use it for SET hardness screening and problem fixing.

Speaker: Mr Staf Verhaegen (imec)

Paper AMICSA2018_DARESETSimulationEnvironment_Paperv2.pdf

Slides AMICSA2018_DARESETSimulationEnvironment_Presentation.pptx

12:35 → 14:00 Lunch

14:00 → 15:15 Radiation Hardened Technologies: (3/3)

Radiation-hardened technologies for analogue and mixed-signal ICs

Convener: Mr Frank Henkel (IMST)

14:00 ESS180RH: An 180nm digital library addressing Single Event Latch-up based on X-FAB XH018

European Sensor Systems S.A is a global developer and manufacturer of high quality sensors based on MEMS. In the course of an ESA activity, titled “Space Qualified Family of MEMS Pressure Modules for Satellite Applications”, European Sensor Systems S.A is developing a custom radiation-hardened capacitive sensor signal conditioning ASIC for interfacing with the MEMS pressure sensors. The ASIC is built using X-FAB XH018 Process Design Kit, a 0.18 micron Modular Mixed Signal HV CMOS Technology. This paper presents a detailed procedure for radiation mitigation against Single Event Latch-up (SEL) effects at physical implementation level and the results of the irradiation campaign at UCL cyclotron. A SEL is the result of the triggering of a parasitic thyristor (PNPN or NPNP structures) mainly existing in CMOS circuits. When it occurs, a high current flows from voltage supply to ground and if the power supply is maintained, the device can be destroyed by thermal effect. The mechanism is well documented in the literature [1]. In the analog part, preventing latch-up from occurring was done by reducing the gain of the two parasitic transistors by increasing the distance between the two parasitic complementary transistors where possible, reducing parasitic well and substrate resistors by using low resistance ground contacts and by surrounding MOS transistors with guard rings. In practice, all PMOS devices have been enclosed by N-type guard rings and all the NMOS devices have been enclosed by P-type guard rings. For the digital part a SEL immune library was required. At that time, the IMEC DARE180X [2] was under development and not fully tested, so it was decided to build a custom on-site library immune to SEL allowing full control of synthesis and place and route procedures. The library ESS180RH consisting of digital cells has been designed and characterized in house to enhance radiation tolerance. It is a 3.3V junction isolated, low power library and contains combinational (logic gates), sequential (scan flip-flops) and special cells (layout fillers, antenna protection cells, level shifters). In the layout the triple well NMOS and PMOS devices have been surrounded by P-type and N-type guard rings respectively. The increase of the layout area compared to a conventional cell varies from 2x to 4x. More specifically, after the layout of each cell is finished, a Library Exchange Format (LEF) file is generated, which includes design rules and abstract information about the cells. An RC parasitic extraction is performed in order to obtain an extracted netlist for analog simulations. The purpose of this step is to perform the modelling of interconnects (resistive and capacitive parasitics) and capturing of the Layout Dependent Effects (LDE) that affect the transistor characteristics and depend on layout placement. The extracted netlist of each cell is then used to perform analog simulations. The output of this step is the creation of the Liberty™ library format, which is an ASCII representation of the timing and power parameters associated with each cell. The timing and power parameters are obtained by simulating the cells under a variety of conditions (Process Voltage Temperature) corners and are used for static timing analysis and power analysis. It contains timing models and data to calculate I/O delay paths, timing check values, interconnect delays. The structure of the .lib file is quite complex. The detailed description of the .lib file and the derivation of the timings is out of the scope of this document. Instead some important aspects are described here for the combinational and sequential cells. The timing characterization is performed using a two-dimensional timing model where the two independent axis variable are input slew and output load capacitance. This means that a two-dimensional matrix is created for each metric, where each row corresponds to the Input Slew and each column to the Output load capacitance. The ASIC was manufactured and tested for SEL in the UCL cyclotron accelerator facility at worst case conditions (maximum voltage supply 3.6V, 85 °C). The ASIC exhibited immunity when the heavy ions shown in Table 1 were used as irradiation sources. ![enter image description here][1] To conclude with, preventing SEL to occur demanded interventions at physical level. For the analog part the solution is quite common. As far as the digital part is concerned, a new 3.3V digital library ESS180RH has been created based on custom layout, parasitic extraction, simulation of the cells and generation of appropriate timing and layout files. The procedure for the creation of the library is fully automated and script-based once the layout is completed and can be easily applied to other foundries or PDK flavors. 1. European Cooperation for Space Standardization, Space product assurance, Techniques for radiation effects mitigation in ASICs and FPGAs handbook, ECSS-Q-HB-60-02A, September 2016 2. IMEC, DARE180X, http://dare.imec-int.com/en/technologies/dare180x [Accessed on 10/2/2018] [1]: https://i.imgur.com/QTwQScr.png

Speakers: Mr Dimitris Mitrovgenis (Senior IC Designer), Mr Theodoros Athanassopoulos (Technical Director)

Slides ESS-AMICSA-2018.pptx

14:25 Mixed-Signal Test Vehicle in Microchip Atmel ATMX150RHA

Introduction ------------ A test vehicle has been designed and tested by Airbus Defence and Space and CNES to evaluate the ATMX150RHA technology from Atmel Microchip. The design and test have been fully subcontracted to Weeroc. A 16-bit 10MSPS dual DAC and a series of analogue switch compose the main core of this test vehicle. On top of these main features, a selection of high voltage transistors, capacitors and resistors from the analogue library has been added for further total dose irradiation test. Fast LVDS transmitter and receiver from Atmel new 3.3V I/Os library have been added to characterize these new I/Os. 16-bit DAC Description ---------------------- The 16-bit DAC has been specified by Airbus Defence and Space. The main requirements are 16-bit parallel input, differential current output, embedded trimmable current reference and multiplying DAC capability, from 4 to 12 MSPS. The chosen architecture based on these requirement has been a mixed of binary and thermometer current steering DAC. The binary part is driving the 12 less significant bits while the thermometer structure drives the 4 most significant bits. A large array of transistor composes the main current source of the DAC. This array distributes semi randomly the current to any of the output of this DAC. Dummy transistor structure allows mismatch reduction in the current sources. The size of the array has been kept small to allow DAC multiplication capability at rather high frequency. A trade-off between output non-linearity and switching speed is required which translates into optimising the transistor mismatch and parasitic capacitance reduction. The current switching part is composed of latency-controlled buffer and binary-to-thermometer converter followed by an array of scaled latches. The latches control injected-charge compensated switches allowing to draw current in positive or negative branch of the analogue output. Voltage and current references are provided by a bandgap structure and a programmable current source. The DAC is biased in 1.8V. Internal voltage regulators allow 3.3V to 1.8V conversion. Architecture and measured performances will be presented in this paper. Fast Analogue Switch -------------------- The fast analogue CMOS switch has been specified to have a 500MHz bandwidth with a below 20 Ohm Ron. The switch must be 5V compatible and shall have a transition time below 20ns. It has been designed to be both 3.3V and 5V compatible with a 1.8V or 3.3V control signal. Several configuration of that switch including a T structure has been embedded and tested in the test vehicle. Measurement results on that switch will be presented in the paper. Conclusion ---------- This paper is aimed to present silicon measurement of a first test vehicle in a promising mixed signal technology widely used in automotive industry and qualified for space application. That test vehicle is a first step towards a unified and qualified European analogue IP library. Promising results and future development plan will be presented.

Speaker: Mr Julien Fleury (Weeroc)

Slides AMICSA18_Weeroc_20062018.pdf

14:50 DARE180U New Analog IPs

In the context of the microcontroller project developed for Cobham-Gaisler, IMEC extended and improved its IPs portfolio of the DARE180U library: * 11 bits SAR ADC * Extended input range PLL * Cristal oscillator * Power On Reset * 1.8V and 3.3V voltage monitor * GPIO with local Power On Control * High density SRAM All these IPs are hardened as the rest of the DARE180U library against radiation and heavy ions. If not explicitly defined the hardening level is respectively 300 krad for TID and 60 MeV*cm2/mg for the LET. **High density SRAM (DARE180U_HDRAM)** This dual port SRAM uses only 1.8V straight transistors in order to reduce the memory cell area. All the other hardening techniques against leakage between N-type regions and against latch up are kept. This IP has a fixed size of 4096 words of 39 bits for a total area of 2032x2180 µm2. **GPIO with local POC (DARE180U_GPIO)** This general-purpose IO can be used as: * Digital input (Schmitt trigger) with programmable pull up/down * Digital output (4mA) * Analog input (serial impedance of 50 Ohms) * Analog output This IO when configured in digital input/output mode is completely SET free and uses only ELT layout for the NMOS transistor to make it insensitive to radiation effect. Its local Power On Control forces the IO output in high impedance mode as long as the core voltage is not turned-on. Practically this high impedance mode will be maintained after the ramp-up of the core voltage thanks to the Power On reset. **Voltage monitor (DARE180U_VMON)** This block monitors the value of the 3.3V and 1.8V supplies. The detection threshold can be adjusted thanks to 3 bits of configuration from 1.6V till 1.77V for the 1.8V version and from 2.9V to 3.24V for the 3.3V version. To avoid false triggering due to noise on the supply a filter drops out any glitches shorter than ~20µs. **Power On Reset (DARE180U_POR)** The power on reset block generates a long reset pulse during the power-up of the core supply. The reset pulse duration can be adjusted thanks to an external capacitor. The typical pulse duration value is 235µs without external capacitor and 150ms with an external capacitor of 220nF. Considering the importance of the reset signal, this IP is obviously also SET free till 60 MeV*cm2/mg. **Cristal oscillator (DARE180U_XO)** The crystal oscillator delivers a stable CMOS level clock signal, using a crystal as input. The XO can be used with a 5 MHz and 25 MHz crystal. The oscillator is hardened against radiation but also against SET: no false edges on the clock can appear and the maximum period error is of 1.1ns and 3.8ns when respectively running at 25 MHz and 5 MHz (60MeV*cm2/mg). **Extended input range PLL (DARE180U_PLL_EXT)** The Phase-Lock-Loop (PLL) IP generates an output clock frequency that is an integer multiple of the input signal frequency. The ratio between the input frequency and the VCO frequency can be programmed to 8, 16, 20, 32, 40 and 80. The VCO of this PLL has been optimized from hardening point of view when running at 400MHz. At that VCO oscillation frequency, the maximum PLL output phase error due to a SET (60MeV*cm2/mg) is of 160ps and no false edge can appear. In absence of SET the PLL output signal has a jitter of 600fs in typical conditions. **11 bits SAR ADC (DARE180U_ADC)** This IP is composed of mainly 2 blocks: * An analog mux 4:1 combined with an auto zeroed-amplifier (0dB, 6dB and 12dB). * A differential and single ended SAR ADC (11b, 300kS/s) with internal voltage reference. All the digital is hardened against SET and SEU: * Use exclusively rad-hard FF (HIT). * The data out bits are SET free thanks to a Muller-C filter. * Clock path hardened by drive strength. * The signals driving the switches connecting the capacitor to the voltage reference are not SET free till 60 MeV*cm2/mg, but any SET on these signals will be filtered thanks to the limited analog bandwidth. The capacitor matrix and their switches are insensitive to “SEU” (i.e. permanent capacitor charge error) except on the capacitor bank side connected to the comparator. Indeed, if during the conversion a charge is injected when the switches connecting the capacitors to the voltage references are on, this charge is stored in capacitor bank. The sensitive junction area of these switches is in differential mode of 2*120µm2, this represent only few event on the total duration of a space mission. The comparator itself is not completely immune to SET but its cross section is quite low and represents only few events (threshold 1 LSB) during one complete space mission.

Speaker: Mr Laurent Berti (IMEC)

Slides

• AMICSA2018_DARE180U_IP_v1.5.doc
• AMICSA2018_DARE180U_New_Analog_IPs_v1.2.pdf
• AMICSA2018_DARE180U_New_Analog_IPs_v1.3.pptx

15:15 → 15:45 AMICSA: Farewell

15:15 Wrap-Up and Finish

Speakers: Mr Boris Glass (ESA), Mr Steven Redant (imec)

Slides AMICSA2018_wrap_up.pdf