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The 16th ESA Workshop on Avionics, Data, Control and Software Systems (ADCSS) covers topics related to avionics for space applications, in the form of a set of round tables. The workshop acts as a forum for the presentation of position papers followed by discussion and interaction between ESA and Industry and between participants. Each theme part of ADCSS workshops will be first introduced and then expanded by presentations on related developments from technical and programmatic points of view. A round table discussion may follow, concluded by a synthesis outlining further actions and roadmaps for potential inclusion into ESA’s technology R&D plans.
All material presented at the workshop must, before submission, be cleared of any restrictions preventing it from being published on the ADCSS website.
Please find the Online access and Wifi details here (restricted to participants).
Presentations will be made available at the end of each day.
The presentation will introduce the Space Avionics Open Interface (SAVOIR) initiative, the main outputs, the status on the work plan, and the trends, as an introduction to the following working group specific presentations.
The presentation reports on the progress of the SAVOIR working group related to Fault Detection, Isolation and Recovery (FDIR). After the publication of the first version of the FDIR Handbook, the new version will address lessons learned from satellite manufacturer and mission operators , and characterize better the guidelines applicability to missions, adding considerations for new missions such as Close Proximity Operation, high autonomy, or use of Artificial Intelligence.
The presentation introduces this new SAVOIR working group, motivated by the recent use of the protocols above the space data link layers, such as CFDP, Bundle Protocol and LTP. These protocols challenge the architecture of the communications function, which will become central, multi-protocol and multi-link. SAVOIR must study and evaluate the impact on the reference on-board architecture, as well as the impact on operations,
The SAVOIR-Autocode working group has produced last year a handbook on the autocoding of Simulink models. It includes a set of cosing guidelines. ESA has entrusted TAS to implement the corresponding rule checker, that is the subject of this presentation.
Located at the cross road of Model Based System Engineering and Avionics, the Electronic Data Sheet is a key exchange format between disciplines and in the Supply Chain, materializing the concept of "exchange' or "interface" of the Space System Ontology. Many work have been done around EDS, whether in CCSDS standardisation, in SAVOIR investigation, or in some project utilisation. The presentation gives an overview of the status and present the roadmap proposed by the SAVOIR Advisory Group.
A workshop should have been held on 24/10 (the day before), aiming at gathering the CubeSat and the SAVOIR community in an attempt to investigate how SAVOIR could benefit and help the CubeSat avionics. The presentation is a debriefing of this workshop.
Two new ECSS standards will soon supersede the still in effect ECSS-Q-ST-60-02C (2008) “ASIC and FPGA development”:
These two new standards will finish going through Public Review in Oct 18th 2022, therefore anyone can review the drafts and submit request for changes until then. After that date the standard drafts will undergo final corrections and improvements in order to be published by ECSS as soon as possible (end of 2022 we hope). An ECSS WG integrated by more than 35 experts from industry, ESA, CNES and DLR, has worked meticulously during 3 years to produce these two complementary engineering and PA standards. These standards will be made applicable for developments of ASICs, FPGAs and IP Cores to be used in ESA projects and technology R&D activities. Engineering and PA requirements have been separated in these two books. This promotes that the supervision of the chip or IP development is done in parallel by engineering technical officers and PA officers from both, the customer and the supplier side. My presentation will summarize the main differences in content and format with respect to the old standard. Some important differences are the new and improved requirements related to HW-SW co-engineering, mixed-signal ASICs, development and re-use of IP Cores, flexibility in the development flows, new chip engineer-friendly terminology for key milestone reviews, default pre-tailoring according to “criticality category” and the type of “DEVICE” (digital ASIC, analog ASIC, FPGA or IP Core) to be developed.
In parallel of the ECSS standardisation for ASIC, FPGAs, and IPCores, the Space Software Engineering Standard ECSS-E-ST-40C has been revised. Some harmonisation has been done, but also several new topics are now addressed in this Revision 1. The presentation presents a synthesis of the changes implemented in the latest revision of the ECSS software engineering standard.
The presentation gives a flavour of the work perform by the Competence Domain 3 to produce the Avionics contribution to the TDE plan 2023-2024 and the GSTP compendium.
The SAVOIR Reference Architecture had been made with the background of an existing physical architecture based on an OBC, RTU and Mass Memory boxes. The model based technique allows to separate clearly the functional and the physical architectures, and to identify the functional chains within the avionics. The presentation introduces the Capella modelling performed in view of updating the SAVOIR documentation towards a more strictly functional view.
The variability observed in the various Power subsystem architectures in projects works against the notion of product line that SAVOIR promotes. In a similar way as the functional avionics, the SAVOIR-Power group performed a model based functional reference architecture of the Power subsystem, subject to this presentation.
Several models are now used to develop the avionics, from the system models (MBSE) to the Avionics models presented before, and up to the Software models (MBSwE) and the microelectronics models. To ensure the consistency between these models along the development life cycle, the digital continuity must be established. The presentation introduces the various elements that have been investigated, in particular in HW/SW co-engineering, to make this continuity.
This session addresses the benefits and challenges of the digital continuity system-avionics-hardware-software, through the experience and needs of the SAVOIR Advisory Group members, as a panel discussion
Companies that are exhibiting are welcome to do a flash presentation about their products and solutions.
Recent advances in Earth observation, embedded computing and machine learning optimisation have led to an increasing number of demonstrations of “on-board AI”, showcasing such applications as cloud detection,ship tracking and disaster monitoring. However, there still exists a disconnect between the outputs of such applications and the real needs of end users.
In collaboration with Surrey Satellite Technology Ltd (SSTL) and the University of Surrey (UoS) under ESA InCubed funding, Craft Prospect is consolidating its software solutions for on-board data processing andinformation extraction into a modular and rapidly-configurable framework – the Astral Intelligence Toolbox (AITB). The AITB employs a component-based design that allows new applications to be configured quickly from customer use cases and requirements. A cloudmasking component can easily be re-configured for land cover classification tasks. Pre-processing tasks can be integrated into the application to handle radiometric calibration, band co-registration and georeferencing as required. Traditional and machine learning-powereddata products can be generated, harmonised and compressed to meet customer requirements on content, accuracy, latency and throughput. Each component is configured such its properties and behaviours work in concert with others to deliver a solution that meetsthe mission needs.
This approach also improves the ability to assure the performance and functionality of configured applications. Components are verified and assured on the unit level, allowing application testing to focus onintegration and end-to-end testing. Machine learning processes developed with the Assuring Autonomy International Programme ensure that the models powering information extraction tasks are developed with a focus on explainability, interpretability and robustness.
Under InCubed funding with SSTL and UoS, three applications – defined through customer engagement and configured using the AITB – will be deployed and demonstrated on SSTL’s Flexible & Intelligence Payload Chain(FIPC). The modular nature of the AITB also makes it portable; applications can be deployed on embedded Linux, SpaceCloud and other platforms.
In this talk, the philosophy, driving requirements and design of the AITB will be presented. Preliminary results from the InCubed activity will be presented and discussed in the context of customer use cases. Finally, a roadmap will bepresented on the AITB’s continued development to target further use cases and mission-critical on-board activities.
New generations of spacecrafts are required to perform tasks with an increased level of autonomy. Space exploration, Earth Observation, space robotics, etc. are all growing fields in Space that require more sensors and more computational power to perform these missions. Furthermore, new sensors in the market produce better quality data at higher rates while new processors can increase substantially the computational power. Therefore, near-future spacecrafts will be equipped with large number of sensors that will produce data at rates that has not been seen before in space, while at the same time, data processing power will be significantly increased.
Use cases like guidance navigation and control applications, vision-based navigation has become increasingly important in a variety of space applications for enhancing autonomy and dependability. Future missions such as Active Debris Removal will rely on novel high-performance avionics to support image processing and Artificial Intelligence algorithms with large workloads. Similar requirements come from Earth Observation applications, where data processing on-board can be critical in order to provide real-time reliable information to Earth.
This new scenario of advanced Space applications and increase in data amount and processing power, has brought new challenges with it: low determinism, excessive power needs, data losses and large response latency.
In this talk, a novel approach to on-board data processing and artificial intelligence (AI) is presented that is based on state-of-the-art academic research of the well-known technique of algorithm pipelining. This technique has seen a resurgence in the high-performance computing work due its low power use and high throughput capabilities. The approach presented here provides a very sophisticated threading model combination of pipeline and parallelization techniques applied to heuristic algorithms (e.g., encryption) and deep neural networks (DNN), making these type of AI applications much more efficient and reliable. Klepsydra software has been validated in an ESA activity with several algorithms and two different onboard computer architectures. The results show that the data processing rate and power saving of the applications increase substantially with respect to standard solutions.
The next generation of the Onboard Computers(OBC) targeting the “New Space Market” will involve the use of Commerical Off The Shelf (COTS) components along with Radiation Tolerant (RT) components. The COTS devices are targeted to provide high performance along with Quality of Service (QoS), high functional integration with a smaller form factor (ideally in a single chip), while the critical and essential functionalities are handled by the RT components. An effective system architecture combining these devices together along with a robust Fault Detection, Isolation and Recovery (FDIR) techniques increases the total availability of the satellite without compromising the core functionalities and performance, offering a cost-effective solution.
EVOLEO Technologies, Germany and AIRBUS Defense and Space, Germany in the frame of the ESA GSTP project CHICS, are developing a full SAVOIR(Space Avionics Open Interface Architecture) compliant and Advanced Data Handling Architecture (ADHA) compatible, radiation tolerant 3U, dual lane OBC, based on the RT Polarfire and Zynq Ultrascale+ Multi Processor System on Chip (MPSoC).
The MPSoC consists of 4 Application Cores (APU), 2 RealTime cores(RPU), Programmable Logic, together with the Polarfire FPGA and multiple memory resources , this infrastructure supports mixed criticality applications typically required for any satellite. The OBC leverages the rich development infrastructure from Microsemi and Xilinx Development platforms, FreeRTOS for RealTime cores, Petalinux for Application cores, Inter Processor communication(IPI) and opensource tools such as XEN Hypervisor for virtualization, ARM TrustZone, Memory and Peripheral protection units controlled by software. These resources aide in developing a comprehensive and reliable software, along with layered FDIR strategy including redundancy, this effectively provides the optimum time and space partitioning required for the essential platform functions and high-performance payload applications. The OBC offers determinism at a system level, allowing flexible processing capabilities such as Symmetric Multiprocessing(SMP) on the APU, resource sharing with RPU, Asymmetric Multiprocessing(AMP) using IPIs, dedicated cache lines to access memory space using hypervisor, leveraging these features will improve the Worst-Case execution time (WCET) and latency of isolated individual functions.
Airbus is one of the first players to introduce commercial off-the-shelf (COTS) components into its mass storage portfolio, such as non-volatile Flash memories, now widely used in many space products.
This choice was motivated by a growing demand for on-board data storage, which could not be met by available space-grade components.
The second generation of Airbus Flash mass memories is already operating in orbit and offers state-of-the-art performance in terms of memory capacity, data-rates, image compression and security.
With two operational satellites already in orbit, the very high resolution 30cm Pléiades Neo constellation of Airbus, exploits the CORECI2 mass memory with great success.
Markets are even more demanding for the next generation of Earth observation satellites that will be flying at the end of this decade.
With the evolution of performance and resolution of instruments requiring a considerable increase in data for storage and processing, the next generation of mass memories will embed a package of new technical solutions.
This presentation will first present the specificities and challenges of mass memories designed for Earth Observation, it will also refer to the state of the art of the generation flying on Pléiades Neo.
In a second step, some perspectives for the next generation of mass memories will be presented, in particular the expectations in terms of performance and associated technologies.
Finally, an overview of the Airbus Mass Memory roadmap will be presented.
Tesat is one of the major suppliers of RF and optical downlink solutions in Europe. The key component of RF downlinksis the so-called Modulator, which encodes and modulates the downlink data onto an RF carrier either in X-band or Ka-band. Within the last 20 years, TESAT has developed various X-band and Ka-band Modulators which are flying on LEO earth observation satellites(e.g. Biomass), GEO communication satellites (e.g. EDRS) as well as on a L3 mission (JWST).
The latest development is the so-called Gigabit Modulator (TETRA) . This modulator is able to transmit user data ata rate of to 2 Gbps either in X-band or Ka-band. It applies the CCSDS 131.2-B-1 standard and supports ACM and VCM operations. Flight models of the Gigabit Modulator are currently in manufacturing for the Copernicus Expansion missions.
TESAT was part of the Hi-SIDE consortium who developed and built up a demonstrator of a high speed on-board network.This network is based on SpaceFibre. It allows to route data between on-board equipment (e.g. instruments, mass memory, modulators) at data rates up to 40 Gbps.
Recently the development of the new generation of the Gigabit Modulator (TETRA-NEXT) has been started. This Modulatorwill be able to transmit downlink data at a rate of 6.3 Gbps per channel. It will be equipped with an optical data interface.
TESAT is also building Laser Communication Terminals for direct-to-earth transmission in cooperation with the Instituteof Communication and Navigation of the German DLR. This has also been part of the Hi-SIDE activity. Therefore the same solutions will also be applied to these products.
In this paper/ presentation an overview of the existing downlink equipment and the new developments at TESAT with focuson the data interfaces will be provided.
The imaging sensor market for space is experiencing a rapid growth largely focused on larger area sensors and faster frame rates. This brings challenges in terms how to output a great quantity of data at high speed in a way that it is still easy to interface with the rest of the system and within a reasonable power budget. These challenges are also present in non-space commercial markets. It is possible to take advantage of advances in electrical interface technology from commercial products to meet the demands of space applications.
The route to support such rapid evolution is to innovate on technologies including the electronic integration. Teledyne-e2v will present the results covering the latest electrical interface innovations for large and high-speed CMOS image sensors and their associated front-end electronics.
CMOS image sensor are now used for the majority of space missions and continue to offer both improved performance and new features. The latest large area platform, CIS300 a 9k x 8.6k 10 µm pixel pitch detector featuring high speed, high dynamic range and ultra-low noise technology enabling sub electron performance, will be presented. The focus will be on the implementation of its 2 Gbps electrical interface. This interface has been developed with the integration of a GHz PLL, serialiser, 8/10B encoding, data stream approach where data, clock, end of line, beginning of line and CRC are included to support high speed through put with high quality. The 2 Ghz output video channel is made of a wide-band low power high speed CML output buffer. A second product, CIS125, utilising this interface will be presented along with silicon results. This is the latest product from the CCDonCMOS charge domain family for high resolution earth observation with a high full well capacity of 30 ke- for a 5 µm pixel pitch.
Examples will be given of how these detectors combined with front-end electronics developed at Teledyne e2v provide performance optimisation and allow easier interfacing with space interface standards.
In 2023, iXblue will release the space-qualified Astrix NS. Astrix NS is a 3-axis gyroscope that covers the needs of the future space missions: compact, cost-efficient, versatile without compromise on reliability and performance. Astrix NS is the latest member of the Astrix family that have demonstrated 6 000 000 hours of cumulated flight in-orbit without incident.
In this presentation and following the successful CDR of June 2022, iXblue will show the latest results of the Astrix NS including inertial performances and validation of the main environments as vacuum, thermal cycling and shock/vibrations. We will also unveil the IMU version, based on Astrix NS architecture and including iXblue accelerometers. Finally, we will present various potential uses of Astrix IMU and gyroscope for missions like orbital maneuvers, orbit rising or planetary landing.
Astrix NS is supported by CNES and designed by iXblue with the support of Airbus Defence & Space for the space qualification.
Thales Alenia Space in the UK has been developing the SiREUS family of inertial sensors for over 15 years, with successful deployments includingCryosat 2, Sentinel-3, MTG and ExoMars rover.
The SiREUS GM20 is the latest evolution in the inertial family. It is a cost-effective, coarse-to-medium performance three-axis gyro for longduration missions of 10 or more years in adverse radiation environments including MEO/GEO. It comprises three MEMS rate detectors, each controlled by a dedicated Thales Alenia Space DPC microcontroller. The use of microcontrollers in place of FPGA and discreteanalogue conversion electronics has allowed significant cost reduction, whilst also providing enhanced observability/maintainability and the option of alternative bus interfaces including UART, CANbus and Mil-1553B. The selective use of up-screened COTS componentsprovides additional cost reductions.
High control loop iteration rates (up to 14 kHz), together with the relatively low clock rates achievable with the current generation of rad-hard processors, present a schedulability problem for a single-core microprocessor, as the numeric processing is a hard real-time activity that would not tolerate asynchronous interruption by the command/control interface. The DPC is uniquely well suited to thistype of application, as it is possible to allocate the real-time algorithm tasks and the asynchronous communications tasks to physically separate cores.
The SGM20 has been baselined for Space Inspire, the next-generation communications satellite platform which is being developed in partnershipwith ESA/CNES. EM models have been extensively tested since 2021 and shown to give equivalent or better performance than the previous generation. EQM and FM models are planned in 2023.
The presentation discusses the architecture and technology of the SGM20 and the rationale for some of the design decisions that resulted in agyro that can be integrated by 3rd parties. It provides details of the achieved gyro performance and its applicability to the next generation of telecom satellites and constellations.
Since 2021, Airbus and iXblue have teamed up to develop the Astrix 200+, with the support of CNES. The Astrix 200+ will be the new member of the Astrix family of gyros that has demonstrated more than 6 000 000 hours of cumulated flight in-orbit without anomaly.
The development investigates the current state-of-the-art of the technology to break through the current model limitations, define a new design and qualify by 2026 the highest performance space gyro yet to come.
The talk will present the main target performance and the comprehensive development plan set up to achieve qualification. It will also discuss the foreseen applications for this equipment.
Demand for high-performance and low SWaP (size weight and power) MEMS accelerometers able to withstand harsh environments is increasing in the space, aviation and defense market due to their inherent advantages versus legacy technologies (e.g., quartz servo accelerometers) and the proliferation of monitoring and control application requiring sensors.
Safran Sensing Technologies Switzerland (Safran STS) proprietary MEMS technology is the ideal a low SWaP, rad hard and reliable solution for the space market, by addressing the performance requirements while levering significant size, power, cost and robustness. Safran STS develop a closed-loop MEMS accelerometer to meet the requirements of a rad-hard accelerometer for incorporation in a low-resource standalone three-axis MEMS accelerometer or Inertial Measurement Unit. Such sensor is mainly adapted for control & navigation purpose like such as entry descent and landing, rover navigation, monitoring and control, and unmanned aerial vehicles.
Our proposed MEMS closed-loop accelerometer is well positioned to meet or exceed the majority of the identified mission requirements. For example, the bias and scale factor residue over temperature have been improved by a factor of at least 5 with regards to high-performance open-loop architecture. The initial BOL bias and scale factor stability values of better than 300µg and 300ppm, respectively, have been demonstrated. The recent developments and innovations in MEMS architecture, packaging, and closed-loop electronics leading to radiation hardness and performance improvements will be presented.
Nowadays, due to the increasing amount of satellites of different types to be orbited and the high cost of the launching missions, the manufacturers are demanding lower cost units that could operate, with similar performances and reliability that the traditional space hard-rad units. NAVIGA is an electronic sensing/processing unit that responds to these needs and will provide a GNSS-INS hybrid navigation solution to the GNC subsystem of the VEGA-C launcher and the Space Rider System. Besides, most launcher manufacturers are evolving their systems, for example, to be able to recover the first stages, to re-use their upper stages to provide in-orbit servicing, and to include additional kick-stages to reach higher orbits (e.g. GEO, Escape, Moon). Through its modular configuration, NAVIGA can be adapted to the needs of these transportation systems, providing a common physical unit which can operate and meet the requirements for all of them.
The NAVIGA development started in 2017, driven by the risk of obsolescence of the former VEGA navigation unit, its high recurring cost, and the potential orbital injection performance increase that could be achieved with a hybrid GNSS-INS system.
The NAVIGA unit is currently under development, close to concluding the Phase C, with an EM available for testing the unit functionality. Since the beginning, the recurrent cost (RC) and the modularity have been one of the main requirements of the NAVIGA unit. The design of an unit capable to achieve the same performances than similar space navigation units with a reduced recurrent cost has been possible by combining the knowledge and experience in space navigation solutions together with the know-how in developing high-precision harsh-environment aviation products. Through its modularity and growth capabilities, NAVIGA can be configured to different missions by replacing the quality of the components, interfacing to external sensors (e.g. STR, radar altimeter),and providing different navigation solutions (GNSS, Inertial and Hybrid). Future NAVIGA evolution will focus in expanding its market, by adding new features compatible with its modularity, without changing its physical characteristics and envelope. With these new features, NAVIGA plans to address several types of missions and applications to consolidate its position as a reference navigation unit for space transportation systems.
NAVIGA is a full European product that ensures the non-dependability from ITAR restriction nor from third party rights and obligations. NAVIGA is presented as a fully European navigation unit that responds to demanding performance requirements and recurrent cost for the vehicle composing the VEGA Space Transportation System (VSTS), with a flexible architecture that can be easily adapted to other environments and space transportation missions.
ARIETIS-NS is a Rad-Tolerant, space qualified 3-axis gyro, whose main applications are Telecom (15+ years GEO), Earth Observation as well as Science and Exploration missions. It mostly uses commercial EEE upscreened components. ARIETIS-NS is being qualified to ESA ECSS standards, meeting the most stringent space quality requirements. ARIETIS-NS is based on Innalabs proprietary Coriolis Vibratory Gyroscope (CVG) technology which is largely used in commercial products for land, marine, and aerospace applications.
ARIETIS-NS has already been selected for a variety of applications, including, but not limited to Earth Observation, Telecom, Exploration, Science, spanning, LEO, GEO, and heliocentric orbits. Thanks to the support of the European Space Agency, the development of ARIETIS-NS is now complete and qualification testing is ongoing with target completion date in Q4 2022, ahead of delivery of the first flight models.
ARIETIS-NS is able to provide high performance (ARW <0.005 deg/√hr) and high reliability (~1000 FITs) in a very compact design (~1.2 kg for LEO application) and very low power consumption (<7W). To achieve this, several targeted enhancements and optimizations to InnaLabs gyroscope's design have been introduced, mainly regarding the component selection, the control loops, the compensation algorithms, and an updated Sensing Element design.
After a brief description of the CVG basic principles and an overview of the CVG technical strengths in comparison to competing technologies, InnaLabs will introduce the specification, the key design features, and the budgets of ARIETIS-NS. InnaLabs will assert ARIETIS-NS key performances displaying test results obtained on Engineering Qualification Models (EQMs); these tests include: performance test (bias stability, scale factor stability, noise, and misalignment), mechanical tests (vibration and shocks) as well as thermal vacuum tests.
Future NASA mission applications demand onboard computing performance, power efficiency, and flexibility not available from current products. To address these needs, NASA’s High Performance Spaceflight Computing (HPSC) project is developing a radiation hardened, general purpose multi-core processor. Key HPSC objectives include natural space radiation hardness, fault tolerance, computation performance and extensibility, and power scalability. This presentation will first highlight how advances in spaceflight computing are key to NASA’s envisioned future for advanced avionics. Descriptions will then be provided for NASA mission applications and use cases that demand advanced spaceflight computing. The presentation will then provide an overview of NASA’s HPSC project and how it will address the computational demands of future missions.
Gaisler is a European vendor of radiation-hardened fault-tolerant microprocessor SoCs that develops the LEON and NOEL-V, processor models. The presentation will share Gaisler's view on applying SPARC and RISC-V in space applications. We will provide a status update on the GR740 LEON4FT quad-core SoC and the current development status of the next-generation products GR765 and GR7xV. GR765 is an octa-core SoC, planned to be available with support for both the SPARC V8 and RISC-V RV64GCH instruction set architectures. The GR7xV is a future GR7xV RISC-V multiprocessor SoC.
This presentation will present all types of Microchip processing solutions from stand-alone processors to FPGA SoC developed for space applications. The targeted content will make the status of all type of products or ongoing development from the different product lines in US & in Europe on different type of processing single core or multicore architectures based on ARM or RISCV. We plan to also highlight all the activities managed in Europe or out of US by Microchip around those different products.
For decades, Microchip has provided one of the industry’s most comprehensive space product portfolios of radiation-hardened and radiation-tolerant solutions that include high-performance MCUs, MPUs, FPGAs, memories, communication interfaces, frequency and timing solutions, mixed-signal ICs, custom power supplies, diodes, transistors and RF components. With product development activities and a qualified supply chain in Europe, Microchip is a key contributor to the European space ecosystem, delivering European and ESCC-qualified solutions.
The journey began with a small FPGA device called NG-MEDIUM. Then the first Rad-Hard Cortex R5 Macro is introduced in NG-LARGE. Later, the FPGA became a real-time application-oriented System-on-chip with a huge reconfigurable logic capacity (NG-ULTRA). Now it is time to go one step further and have a complex SoC with Cortex A and Cortex R processors. Thanks to the DUROC project, Nanoxplore has initiated the development of a SoC FPGA - Ultra7 on 7nm FinFET which will be the most advanced process node for space.
The NG-Ultra, commercialized by Nanoxplore, was developed thanks to European joined efforts to offer to Space community for the next decade a System-on-Chip component sized with the necessary processing power, trusted with radiation hardened by design technology, supported by well-supported ecosystem and offering European non-dependence.
Indeed, the Rad-Hard European NG-Ultra implements a quad-core ARM R52, a highly robust DDR controller, High Speed Serial Links, a modern SoC interconnection system and a performant rad-hard FPGA matrix for flexibility and possible in-flight re-programmability. This presentation will allow to explain the reasons why such a product is able to address a range of Use Cases for future Space applications, with a focus on its architecture, key features and processing performances. A status of the ecosystem will be exposed, for both hardware and software development. And finally, perspectives will be shown with a description of a NG Ultra-based processing board under development for a future platform On-Board Computer.
TASinI adopted MultiCore Processor in their On Board Computer since the first announced development of ESA NGMP in 2011 up to the release of first prototype of Quad-Core Leon4FT GR740 SoC in 2015. In this 11 years the IPAC, Integrated Processor and Aocs Controller, On Board Computer family has been developed covering a wide range of space applications; the development covered both Hardware and Software aspects covering several critical aspects induced by the use of such complex architecture. In the meantime, alternative solutions, based on different ISA, have become available, e.g. ARM, and other are coming into the limelight, e.g. RISC-V. This presentation addresses the experience matured in the last decade and the future perspectives from an industrial developer's point of view.
Japan Aerospace Exploration Agency (JAXA) and Mitsubishi Heavy Industries, Ltd. (MHI) have started the development of the next generation micro processing unit (MPU) for space-use. Both high performance computing and low power consumption are important features to realize future missions of spacecraft like satellites and rovers that are becoming sophisticated. We adopted Silicon-on-Insulator (SOI) wafer to achieve very low power consumption and dual-core architecture to realize high performance computing. Since this MPU will be the first device which adopts a dual-core architecture, we’ve also been developing an operating system (OS) that suits for it. I’m going to mention about our future view about this MPU in my presentation.
This session aims to give European Spacecraft LSIs the stage to present their current process, lessons learnt and perspectives on Avionics Functional Verification. Product line specifics wrt Avionics Functional Verification are interesting to address, in view of current and future ESA missions. The recently published ECSS-E-ST-10-03C Rev.1 "Testing" and ECSS-E-HB-10-03A "Testing guidelines" will be considered, as providing new initial baseline for Avionics functional validation process in ESA missions.
This session aims to share ESA lessons learnt on Avionics Functional Verification for SmallSat and Nanosat platforms, in relation to the ESA mission classification. ESA will present guidelines for the development of nanosat AOCS systems elaborated from the technical experience gained on the numerous nanosat missions supported by the Agency, from Education missions to IOD/IOV and operational application missions.
This session aims to present and share with ADCSS audience the activities initiated to prepare for defining reliable verification process of AI-based flight software and AOCS/GNC systems. Related activities are planned for the next couple of years, in particular through the ESA GSTP Compendium on Artificial Intelligence. This preliminary announcement of future and intended activities will close the Functional Avionics Verification session.