TEC-ED & TEC-SW Final Presentation Days - December 2016

6 Dec 2016, 08:00 → 7 Dec 2016, 18:15 Europe/Amsterdam

Newton 2 (ESA/ESTEC)

Kjeld Hjortnaes (ESA/ESTEC - Software Systems Division), Philippe Armbruster (ESA/Data Systems Division)

The Software Systems Division (TEC-SW) and Data Systems Division (TEC-ED) Final Presentation Days are scheduled on Tuesday 06 December & Wednesday 07 December in conference room Newton 2 (ESA/ESTEC, The Netherlands)

All material presented at the workshop must, before submission, be cleared of any restrictions preventing it from being published on this web-site.

 

Tuesday 6 December

08:00 → 08:30 Registration

Speakers: Ms Bertilla Sinka (ESTEC), Kathleen Gerlo (ESA/ESTEC - Software Systems Division)

08:30 → 08:45 Introduction

Presentation 00_-_Introduction.pdf

08:45 → 09:30 Schedulability Analysis Techniques and Tools for Cached and Multicore Processors

Speaker: Mr Panagiotis Katsaros (CERTH)

Abstract 01_-_Schedulability_Analysis_Techniques_...pdf

Presentations 01a_-_Schedulability_Analysis_..._-_Intro_TO.pdf 01b_-_Schedulability_Analysis_....pdf

09:30 → 10:15 Definition and Design of software components for LEON3FT Microcontroller and LEON-REX Instruction Set Architecture

Speaker: Mr Daniel Cederman (Cobham Gaisler AB)

Abstract 02_-_Definition_and_Design_of_software_components_for_LEON3FT_Microcontroller_and_LEON-REX.pdf

Presentation 02_-_Definition_and_Design_of_software_components_....pdf

10:15 → 11:00 OBC Mass Memory (Solid State mass Memory Board/Module Integrated in OBC)

Speakers: Mr Dietmar Walter (DSI), Mr Glenn Johnson (SciSys), Mr Patrick Sandin (RUAG Space AB)

Abstract 03_-_OBC_Mass_Memory.pdf

Presentation 03_-_OBC_Mass_Memory_....pdf

11:00 → 11:30 Coffee Break

11:30 → 12:15 CLP: Control Loop Processor, Architectural Design, Verification and FPGA prototypes

Speaker: Mr Marco Ruiz (SABCA)

Abstract 04_-_CLP.pdf

Presentations 04a_-_CLP_-_Intro_TO.pdf 04b_-_CLP.pdf

12:15 → 13:00 Deploying Plug and Play Avionics

Speaker: Mr Richard Melvin (SciSys)

Abstract 05_-_Deploying_Plug_and_Play_Avionics.pdf

Presentation 05_-_Deploying_Plug_and_Play_Avionics.pdf

13:00 → 14:00 Lunch Break

14:00 → 14:45 Extensions and Validation of Virtual Platform for complex System-on-Chip and IP Cores Design for Space

Speaker: Mr Alberto Ferrazzi (Terma)

Abstract 06_-_Extensions_and_Validation_...pdf

Presentations 06a_-_Extensions_and_Validation_of_Virtual_Platform_...pdf 06b_-_Extensions_and_Validation_of_Virtual_Platform_...pdf

14:45 → 15:30 Space Fibre IP core

Speaker: Mr Felix Siegle (Cobham Gaisler AB)

Abstract 10_-_SpaceFibre_Port_IP_Core.pdf

Presentation 07_-_Space_Fibre_IP_core.pdf

15:30 → 16:00 Coffee Break

16:00 → 16:45 DMON and the AGGA 4

Speaker: Prof. Michael Ryan (O.C.E. Technology)

Abstract 08_-_DMON_and_the_AGGA_4.pdf

Presentations 08a_-_DMON_and_the_AGGA_-_Intro_TO.pdf 08b_-_DMON_and_the_AGGA_[Compatibility_Mode].pdf

Video 08c_-_DMON_and_the_AGGA_-_Video.mp4

16:45 → 17:30 LLVM compiler for in flight SW development and validation process

Speaker: Dr Emil Vassev (LERO)

Abstract 09_-_LLVM_compiler_for_in_flight_SW_development_and_validation_process.pdf

Presentation 09_-_LLVM_compiler_...pdf

Wednesday 7 December

08:00 → 08:30 Registration

Speakers: Ms Bertilla Sinka (ESTEC), Kathleen Gerlo (ESA/ESTEC - Software Systems Division)

08:30 → 08:45 Introduction

08:45 → 09:30 TASTE Multicore

Speakers: Ms Claire Pagetti (ONERA), Mr Jérôme Hugues (ISAE SUPAERO)

Abstract 01_-_TASTE_Multicore.pdf

Presentation 01_-_TASTE_Multicore.pdf

09:30 → 10:15 Improvement of the OSRA SCM Model Editor

Speakers: Mr Andreas Jung (ESA/ESTEC), Mr Goulwen Le Fur (Obeo)

Abstract 02_-_Improvement_of_the_OSRA_SCM_Model_Editor.pdf

Presentation 02_-_Improvement_of_the_OSRA_SCM_Model_Editor.pdf

10:15 → 11:00 Benchmarking Autonomous Robotics Controllers (NPI Activity)

Speaker: Mr Pablo Muñoz (University of Alcalá)

Abstract 03_-_Benchmarking_Autonomous_Robotics_Controllers.pdf

Presentation 03_-_Benchmarking_....pdf

Video https://www.youtube.com/watch?v=9aKTPc1EOQ0&feature=youtu.be

11:00 → 11:30 Coffee Break

11:30 → 12:15 SpaceWire Electrical Testing

Speaker: Mr Brice Dellandrea (Thales Alenia Space - France)

Abstract 04_-_SpaceWire_Electrical_Testing.pdf

Presentations 04a_-_SpaceWire_Electrical_Testing_-_Intro_TO.pdf 04b_-_SpaceWire_Electrical_Testing.pdf

12:15 → 13:00 Multi-threaded processor for space applications

Speakers: Mr Chris Jesshope, Dr Martin Daněk (Daiteq s.r.o.)

Abstract 05_-_Multi-threaded...pdf

Presentations 05a_-_Multi-threaded_processor_for_space_applications_-_Intro_TO.pdf 05b_-_Multi-threaded_processor_for_space_applications_[Compatibility_Mode].pdf

13:00 → 14:00 Lunch Break

14:00 → 14:45 Verification of Computer-Controlled Systems

Speaker: Ms Elena Alaña Salazar (GMV)

Abstract 06_-_Verification_of_Computer_Controlled_Systems.pdf

Presentations 06a_-_Verification_of_Computer-Controlled_Systems_-_Intro_TO.pdf 06b_-_Verification_of_Computer-Controlled_Systems.pdf

VERICOCOS Website http://vericocos.gmv.com/

14:45 → 15:30 Catalogue for System and Software Properties - CatSY

Speaker: Mr Victor Bos (SSF)

Abstract 07_-_Catalogue_for_System_and_Software_Properties_-_CatSY.pdf

Presentations 7&8a_-_Catalogue_of_System_and_Software_Properties_-_Intro_TO.pdf 8b_-_CatSY.pdf

15:30 → 16:15 Catalogue for System and Software Properties - CSSP

Speakers: Mr Panagiotis Katsaros (AUTh), Mr Simon Bliudze (EPFL)

Abstract 08_-_Catalogue_for_System_and_Software_Properties_-_CSSP.pdf

Presentation 7b_-_CSSP.pdf

16:15 → 16:45 Coffee Break

16:45 → 17:30 Enabling FDIR design through diagnosability and recoverability analysis

Speaker: Mr Benjamin Bittner (Fondazione Bruno Kessler)

Abstract 09_-_Enabling_FDIR_...pdf

Presentations 09b_-_Enabling_FDIR_....pdf 9&10a_-_FDIR_+_COMPASS_-_Intro_TO.pdf

17:30 → 18:15 Consolidation of COMPASS tools

Speakers: Mr Harold Bruintjes (RWTH Aachen University), Mr Marco Bozzano (Fondazione Bruno Kessler)

Abstract 10_-_Consolidation_of_COMPASS_Tools.pdf

Presentation 10b_-_Consolidation_of_COMPASS_tools.pdf