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SEFUW: SpacE FPGA Users Workshop, 4th Edition

9–11 Apr 2018
European Space Research and Technology Centre (ESTEC)
Europe/Amsterdam timezone
PLEASE READ ME: public presentations (made available by the presenters) posted on website - for the presentations not available and/or password protected, a public version was not made available by the presenters.

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Contribution List

43 out of 43 displayed
  1. 52. Welcome
    Mr David Dangla (CNES), Mr David Merodio Codinachs (ESA)
    09/04/2018, 10:00
  2. 45. FPGA experience and SoC design methodology at Airbus Defence & Space.
    Mr Ottmar Ried (Airbus Defence & Space GmbH)
    09/04/2018, 10:30
    Since years Airbus Defence and Space capitalizes on the advantages of Field Programmable Gate Array Technologies and has accumulated considerable heritage and experiences with it. This presentation provides with an overview of the application domains and the FPGA devices that address those application fields. That extends from the well-established Microsemi anti fuse FPGAs (RTSX/RTAX) to more...
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  3. 28. Jena-Optronik Experience Summary on Microsemi RTG4 designs
    Johannes Both (Jena-Optronik)
    09/04/2018, 10:50
    Thanks to its robust design and accurate measurements, the Jena-Optronik RVS© LIDAR sensors are the most frequently used rendezvous- and docking sensors for ISS resupply by the European ATV, Japanese HTV and the US-American “Cygnus” transport vehicle built by Orbital ATK. The RVS sensor is limited, though, to rendezvous and docking with cooperative targets, i.e. targets equipped with...
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  4. 37. SpaceFibre, Spectrometer and Camera: Some applications on the RTG4 FPGA
    Prof. Steve Parkes (University of Dundee)
    09/04/2018, 11:10
    STAR-Dundee has extensive experience with demanding applications on the Microsemi RTG4 FPGA. Single-lane and multi-lane SpaceFibre IP cores have been designed and tested on the RTG4 along with other SpaceFibre IP cores. This serial interface IP runs at 3.125 Gbits/s using the internal SerDes of the RTG4. An FFT-based spectrometer has been designed which performs a 1k-point complex FFT at 2.4...
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  5. 8. UVVM - Universal VHDL Verification Methodology. Setting a standard for VHDL testbenches
    Mr Espen Tallaksen (Bitvis)
    09/04/2018, 11:30
    For an FPGA design we all know that the architecture – all the way from the top to the micro architecture – is critical for both the FPGA quality and the development time. It should really be obvious that this also applies to the testbench. Most FPGA designs are split into stand-alone modules – for instance for each of the FPGA external interfaces. In VHDL these modules are VHDL entities...
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  6. 43. Multiple-clock Domain FPGA Designs: Challenges and Solutions
    Dr Reuven Dobkin (vSync Circuits)
    09/04/2018, 12:10
    Inter clock domain crossings inside multiple clock domain design must be treated carefully in order to eliminate synchronization failures and assure design reliability. For space applications, the reliability assurance is crucial, calling for employment of state-of-the art design integration and verification techniques. The problem is exacerbated by the fact that the synchronization bugs...
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  7. 17. RTL Analysis and CDC Analysis for Maximum Design Efficiency and Quality
    Mr Scott Calkins (Blue Pearl Software. Inc)
    09/04/2018, 12:35
    ASIC and System on Chip (SoC) design and verification practices have traditionally been much more rigorous than that of their FPGA counterparts. Mandated by large non-recurring engineering (NRE) fees associated with the manufacturing setup, design teams set up robust verification methodologies that are rigorously followed to avoid errors that could cause an expensive re-spin. With NRE fees in...
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  8. 6. Build and Debug Highly Reliably FPGA-based Designs
    Mr Philipp Jacobsohn (Synopsys)
    09/04/2018, 14:00
    Deploying FPGAs in high-assurance applications makes it necessary to protect the device against malfunction. SEU mitigation and error monitoring circuitry is a mandatory prerequisite for any FPGA design used in high radiation environments. Designing SEU-tolerant circuits can be done in manual or automated ways by introducing design techniques such as triple-mode-redundancy and safe...
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  9. 18. Advanced Verification for FPGAs
    Mr Simone Catenacci (Mentor, a Siemens Business)
    09/04/2018, 14:25
    Emerging design methodologies and increasingly complex FPGAs are creating a need for new approaches to verification to keep pace. As a result, the balance is shifting as more FPGA users want and need to adopt modern verification practices in order to be competitive but don't always know where to start or find the cost/risk too great to embark on. This session will discuss themes in the FPGA...
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  10. 20. Exhaustively Verify SEU Mitigation Techniques Using Formal Verification
    Mr Mark Handover (Mentor, A Siemens Business)
    09/04/2018, 14:50
    In recent years, Formal verification has moved beyond a tool solely for use by experts and into the mainstream.  Now, targeted formal apps’ are lowering the barrier to entry for formal, enabling its use in automated design checking, clock domain crossing analysis and coverage closure to name a few. This session will briefly discuss a range of formal apps’ available before focusing on one...
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  11. 15. Evaluation of MATLAB/Simulink and RTL VHDL HDL environment
    Mr Klemen Bravhar (ESA), Mr Stephan van Beek (MathWorks)
    09/04/2018, 15:10
    The FPGAs for space are growing in complexity and performance and the design time is shortening. There are several high-level synthesis approaches that aim to help FPGA designers increase their productivity. The objective of this work is to assess the MATLAB/Simulink high-level design flow, by using 2 applications from the specification to the deployment into different FPGA platforms. For...
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  12. 26. FUSIO RT: A New Space Modular Computer Core based on Nanoxplore NG-Medium FPGA
    Mr Pierre-Eric Berthet (3D PLUS), Mr Pierre-Xiao WANG (3D PLUS)
    09/04/2018, 15:30
    FPGA based computer unite is quite common in space design thanks to FPGA’s high flexibility, high performance and its short time to market and unit low cost. On the other side, whatever the application is, a SRAM based FPGA need to use the bitstream memory, and most cases computing memory and mass memory to build its eco system. Cooperating with Nanoxplore, 3D PLUS develops a modular...
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  13. 22. Analysis and Mitigation of Single Event Upsets in Configuration Memory of Xilinx Kintex7 SRAM-based FPGA
    Dr BOYANG DU (Politecnico di Torino)
    09/04/2018, 15:50
    Radiation test has been widely used as one of verification methods able to provide accelerated, realistic environment especially for space applications to evaluate device and system reliability against effects induced by charged particles. As for SRAM-based FPGA, one of the popular reconfigurable devices on the market providing high performance and flexibility, Single Event Upset (SEU) in...
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  14. 27. Fault injection for space: FT-Unshades2 updates, experiences and roadmap
    Prof. Hipólito Guzmán-Miranda (Universidad de Sevilla)
    09/04/2018, 16:10
    Fault injection is a promising technique for predicting the SEU Architectural Vulnerability Factor (AVF) of digital designs for space applications. Unfortunately, learning and using fault injection emulation tools needs a time and effort investment that may discourage development teams from applying the technique. Furthermore, there is an understandable concern in the design community about...
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  15. 12. Xilinx On-Orbit Reconfigurable Kintex UltraScale FPGA Technology for Space
    Mr Daniel Elftmann (Xilinx)
    10/04/2018, 09:00
    Space Electronic designers have long desired to have the same capability that terrestrial based electronic system designers have for adaptation, improvement, and flexibility in their digital signal processing architecture. The initial Xilinx Virtex-5 SRAM based Field Programmable Gate Array (FPGA) technology was introduced into the terrestrial marketplace in 2007. The work on the Virtex-5QV...
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  16. 11. First Design-In Experiences of Xilinx's, 20 nm, Kintex UltraScale KU060 for Space Applications and 16 nm UltraScale+ RFSoC for Ground Segment
    Dr Rajan Bedi (Spacechips Ltd)
    10/04/2018, 10:00
    We compare and share design-in experiences of Xilinx's, 20 nm, Kintex UltraScale KU060 for space applications. This FPGA offers 726k LUTs and 32, 12.5 Gbps high-speed serial links, offering the potential to enable the next generation of real-time, high-throughput payloads. The KU060 can instantiate Xilinx's, TMR, MicroBlaze 32-bit RISC MPU for fault-tolerant applications as well as Vivado's IP...
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  17. 14. Single Event Characterization of a Xilinx UltraScale+ MP-SoC FPGA
    Mr Thomas Lange (IROC Technologies)
    10/04/2018, 10:20
    Due to the technology scaling, more and more complex applications can be implemented on configurable devices, such as the new Xilinx FPGAs and MP-SoCs. In addition, devices manufactured in new process technologies, e.g. FD-SOI and FinFet, show a much lower sensitivity to Single Event Effects than previous generation bulk processes. These aspects and their affordable cost, especially in...
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  18. 44. Ultra-High Energy Heavy Ions radiation tests on COTS FPGAs at CERN: results for Microsemi ProASIC3 and Xilinx Zynq all-programmable SoC
    Dr Antonios Tavoularis (European Space Agency)
    10/04/2018, 10:45
    The higher performance requirements of the upcoming space missions and the availability of highly integrated processing solutions, such as the Xilinx all-programmable SoC, calls for an increase in the use of COTS devices and software-defined applications. SEE characterization of these devices is at the same time a necessity and a challenge, because they present difficulties that are either not...
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  19. 13. Microsemi RTG4 Radiation Tolerant FPGAs: Radiation and Qualification Update
    Mr Ken O'Neill (Microsemi)
    10/04/2018, 11:40
    In this presentation we will provide the latest updates on radiation testing and qualification status of Microsemi's RTG4 FPGAs. We will also cover updates on packaging technology and screening flows. A quick overview of updates relating to Microsemi mixed signal standard products for space applications will also be provided, as these products are frequently used in conjunction with FPGAs to...
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  20. 31. Modern On-Board-Processing based on FPGAs for Flexible Satellite Communication
    Mr Florian Rittner (Friedrich-Alexander-Universität Erlangen-Nürnberg)
    10/04/2018, 12:40
    Flexible satellite payloads are important for the use cases of modern satellite constellations. A reconfigurable On- Board- Processor (OBP) based on Field-Programmable Gate Array (FPGA) technology provides the needed flexibility and enables adaptable signal filtering, regeneration, and switching / routing by reconfiguration of the digital signal processing chain. Additionally, new powerful...
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  21. 33. FPGA Based Multithreading for On-Board Processing
    Mr Andrea Guerrieri (EPFL), Mr Bilel Belhadj (Syderal), Mr Pasquale Lombardi (Syderal)
    10/04/2018, 14:00
    FPGA (Field Programmable Gate Array) is an attractive technology for high speed data processing in space missions due to its unbeatable flexibility and best performance to power ratio, in comparison to software. However FPGAs suffer from two major drawbacks. First, higher programming effort is required with respect to software and, second, hardware resources need to be allocated for each...
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  22. 38. Controlling Concurrent Change in Aerospace Electronics
    Dr Björn Fiethe (IDA TU Braunschweig)
    10/04/2018, 14:40
    Space missions have to handle very high data rates due to increased spatial, radiometric and time resolutions of payload instruments already now. To be able to handle this amount of data, final physical values have to be extracted in real time by an autonomous, intelligent and reliable application already on board the spacecraft, adapting itself to the changing needs in a controlled...
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  23. 39. Overlay Architectures for Space Applications
    Dr Jose Sousa (IPbloq)
    10/04/2018, 15:00
    If a reconfigurable architecture is synthesized on commercial of the shelf (COTS) FPGAs it is called an overlay architecture. Overlays are portable, allows the user to abstract from the FPGA resources used, and is orders of magnitude faster to configure compared to FPGAs. In this communication we present an overlay architecture consisting of one or more RISC-V CPUs and one or more IPBloq...
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  24. 32. Review and comparison of design methodologies and hardware implementations on FPGA technologies. Case study: CCSDS compression algorithms for multispectral and hyperspectral images
    Dr Antonio Sánchez (IUMA/ULPGC), Mr Yúbal Barrios (IUMA/ULPGC)
    10/04/2018, 15:20
    Reprogrammable Field Programmable Gate Arrays (FPGAs) for space applications, are becoming steadily more common in space applications due to their high flexibility to change dynamically the functionality of the on-board system, combined with high performance and low power consumption. SRAM-based FPGAs) are vulnerable to radiation, which can cause bit flips in the configuration memory,...
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  25. 9. Image compression on reconfigurable FPGA for the SO/PHI space instrument
    Mr David Hernandez Exposito (Instituto de Astrofísica de Andalucía - CSIC)
    10/04/2018, 15:40
    In this work we present a novel FPGA implementation of the Image Data Compression standard proposed by the Consultative Committee for Space Data Systems (CCSDS-IDC 122.0-B) aboard the Polarimetric Helioseismic Imager instrument of the ESA’s Solar Orbiter mission (SO/PHI). The SO/PHI telemetry constraints enforce the use of specific strategies for on-board data reduction, analysis, and...
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  26. 4. Implementation of Visual Based Navigation in a CPU-FPGA architecture for planetary landing
    Mr Joao Oliveira (Spin.Works)
    10/04/2018, 16:00
    The work presented in this article is the product of an activity with the objective of further develop and flight test visual based navigation (VBN) and hazard detection and avoidance (HDA) algorithms to serve the needs of future Mars and other planetary missions and raise them to a technology readiness level (TRL) of 5 (“critical function verification in a relevant environment”). The...
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  27. 50. Implementation of a GNSS Space Receiver on a Zynq
    Mr Marc Majoral (CTTC)
    10/04/2018, 16:50
    Currently the Agency is using space-qualified GNSS receivers based on ASIC solutions (in particular, the AGGA-family) integrated in ad-hoc instruments (receivers). Such receivers provide outstanding measurement quality required for POD (Precise Orbit Determination) performed on ground, but at the cost of high price and power consumption. In order to address the needs of low cost missions (eg:...
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  28. 10. A Comparison of 65 nm Space-Grade and COTS FPGAs : RTG4 vs. V5QV vs. NG-MEDIUM vs. NG-LARGE vs. IGLOO2 vs. SmartFusion2
    Dr Rajan Bedi (Spacechips Ltd)
    10/04/2018, 17:10
    We compare IP implementation and share design-in experiences of six 65 nm ultra deep-submicron, space-grade and COTS FPGAs: RTG4, V5QV, NG-MEDIUM, NG-LARGE, IGLOO2 and SmartFusion2. Two versions of the RTG4 flash FPGA containing the same rad-hard die are available to the space industry: a 1657 CCGA/CLGA device and a 352-pin CQFP part with less (166 vs. 720) I/O and fewer (4 vs. 24)...
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  29. 24. From eFPGA cores to RHBD SoC FPGA
    Mr JOEL LE MAUFF (NanoXplore)
    11/04/2018, 09:00
    NanoXplore is a privately owned fabless company based in France, created by veterans of semiconductor industry with roughly 30 years experience in the design, test and debugging of e-FPGA cores. Thanks to that background, NX has been awarded a contract by European Space Agencies, ESA and CNES, to develop and to industrialize Radiation Hardened Sram-based FPGA devices under both ESCC and DLA...
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  30. 41. QUEENS-FPGA: Quality Evaluation of European New SW for the BRAVE FPGA
    Mr David Gonzalez-Arjona (GMV Aerospace and Defence)
    11/04/2018, 10:00
    GMV is the prime contractor of QUEENS-FPGA project which stands for “QUality Evaluation of European New SW for brave FPGA”. The BRAVE project supported by ESA and CNES provided very promising European SRAM-based FPGAs for Space, a good roadmap that will allow Europe to avoid restrictions on access to non-European technologies and FPGAs. GMV will present the preliminary conclusions of NG-MEDIUM...
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  31. 40. High-Performance Benchmarking of the European NG-MEDIUM FPGA
    Dr George Lentaris (National Technical University of Athens, Greece)
    11/04/2018, 10:25
    “Quality Evaluation of European New SW for the BRAVE FPGA” (QUEENS-FPGA) is an ongoing ESA activity for the assessment and improvement of the programming tools of the new rad-hard NG-MEDIUM FPGA. Given BRAVE's primary target, i.e., high-performance applications, it becomes imperative to test the tool and device with computationally demanding benchmarks suitable for space missions, such as...
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  32. 25. An ECSS-Q-ST-60-02C compliant verification flow for scientific projects
    Mr Marcin Darmetko (Centrum Badan Kosmicznych PAN (Space Research Centre))
    11/04/2018, 10:50
    Verification of a space project is a complex and time-consuming task due to requirements for high reliability and extensive documentation. Unexpected changes to design are likely to happen in scientific projects, often forcing the whole process to be repeated. Because of these reasons, automation is highly desirable in space FPGA development. The aim of the presentation is to show that...
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  33. 16. Permanent Fault Handling in SRAM-based FPGAs
    Mr Florian Rittner (Friedrich-Alexander-Universität Erlangen-Nürnberg)
    11/04/2018, 11:40
    Permanent faults are a critical issue when using SRAM-based FPGAs in space applications. Compared to tem- porary effects such as Single-Event Upsets (SEUs), a system restart by performing an FPGA reset or a power cycle does not recover these faults. Usually, the occurrence of permanent faults has a low probability but is highly critical as it might lead to a system outage. In harsh...
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  34. 7. Fuzzy-logic simulation based approach to modelling of fault propagation in FPGAs.
    Mr Andrzej Cichocki (Centrum Badan Kosmicznych PAN)
    11/04/2018, 12:00
    Safety-critical digital applications often require calculating the probability of system failure. Existing tools for verification of FPGA-based designs in terms of susceptibility to SEUs/SETs base mainly on fault injection methods, that require numerous runs in order to get proper statistics and are not exhaustive. Run-time of post P&R simulations may significantly limit complexity of analysed...
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  35. 42. Reprogrammable Flash-based FPGA on EUCLID mission
    Prof. Luca Sterpone (Politecnico di Torino), Dr Raoul Grimoldi (OHB ITALIA)
    11/04/2018, 12:20
    EUCLID is a cosmology mission part of Cosmic Vision 2015 – 2025 whose prime objective is to study the geometry and the nature of the dark Universe (dark matter and dark energy). The goal of the mission is to investigate the distance-redshift relationship and the evolution of the cosmic structures by measuring shapes and redshifts of distant galaxies. EUCLID space segment will be a space craft...
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  36. 23. Advancement on the Analysis and Mitigation of SETs on Flash-based FPGAs
    Dr Sarah Azimi (Politecnico di Torino)
    11/04/2018, 12:40
    When particles hit a sensitive region of the ICs, it can lead to the voltage glitch, i.e. Single Event Transient (SET). Flash-based FPGAs are attracting more and more interests due to the immunity of their configuration memory against Single Event Upset (SEU). Flash-based FPGA technologies such as ProASIC3 as the golden core of several space mission project and RTG4 as the newest technology...
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  37. 34. Using Open-source Spacewire and RMAP IPs in the PLATO Router and Data compressor Unit (RDCU)
    Dr Jorge Tonfat (Space Research Institute / Austrian Academy of Sciences)
    11/04/2018, 14:00
    In this work, it is presented how both IPs were adapted and functionally verified for the PLAnetary Transits and Oscillations of stars (PLATO) RDCU. The PLATO mission goal is to detect terrestrial exoplanets around bright solar-type stars and characterize them to determine their habitability. The PLATO instrument is based on a multi-telescope concept. The RDCU is part of the Instrument...
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  38. 35. Virtex5QV - Device & High Speed Interfaces Feedbacks
    Mr DANILO LAMONACA (Thales Alenia Space Italy)
    11/04/2018, 14:20
    The electronic systems are becoming more and more complex and in need of new high performance programmable logic devices, with an increased number of internal resources and high speed interfaces. In TAS-I the Xilinx Virtex5QV device is going to be used on a flight unit and this presentation aims to share with the FPGA space community our experience on two specific aspects : (1) A short...
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  39. 30. Use of FPGAs in a scientific instrument development process: processing, testbenchs, simulators
    Mr Damien Rambaud (IRAP CNRS)
    11/04/2018, 14:40
    I will present the use of FPGA in the different parts of the SVOM/Eclairs project : how they are used in the instrument itself and how we implement prototypes but also how we use them to allow scientists to do more accurate simulations of the instrument by using FPGA based instrument simulator.
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  40. 36. Evaluation of a New Mass Memory Controller Architecture on Space-Grade FPGAs
    Mr Lei Jia (Institute of Computer and Network Engineering (IDA), TU Braunschweig, Braunschweig, Germany)
    11/04/2018, 15:00
    A novel Next Generation Mass Memory Architecture (NGMMA) has been introduced for future space application within the scope of an ESA study (Contract No. AO/1-5975/08/NL/LVH) to cope with the growing demands on very high-speed and huge data volumes of future space-borne instruments. In this context, a new memory controller architecture has been developed and evaluated, which interfaces DDR3...
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  41. 47. Comparison between Microsemi RTG4 and Xilinx SIRF
    Mr Felix Vermersch (SERMA)
    11/04/2018, 15:20
    This talk presents a comparison of the performances between FPGAs XILINX Virtex 5QV and Microsemi RTG4 from a reference space design. It presents the modifications brought to the reference design to adapt it to the new target : the Microsemi RTG4. The problems met in this porterage owed to the differences of the technologies and a comparative degree of the performances on each of the targets...
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  42. 49. Radiation Testing and End User Validation of the BRAVE NG-Medium FPGA
    Mr Luis Berrojo (Thales Alenia Space in Spain)
    11/04/2018, 15:40
    TAS has been involved on the Radiation Testing and End User Validation of the BRAVE FPGA within the frame of the H2020 VEGAS project. TASE is the leader of the radiation test campaign and device characterization. Positive preliminary results indicate that the device is a good candidate for Space applications, although additional campaigns are still foreseen. For End User Validation purposes...
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  43. 5. Design and Prototype Wireless Communications Systems on FPGA/SoC platforms
    Mr Stephan van Beek (MathWorks)
    New applications of wireless communications are growing rapidly – everything is getting connected. Also new standards are emerging such as: 5G, Vehicle-to-vehicle (V2V) and –to-everything (V2X), Narrowband IoT (NB-IoT), 802.11ac, 802.11ah, etc. and this requires adaptability. The ability to adapt requires a way to quickly design, simulate, prototype and upgrade in the field:...
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